Abstract: An adjustable phase clock includes a number (n) of delay circuits having respective controllable delays and being connected in cascade for generating n respective delayed signals. A first delay circuit receives the input clock signal and an nth delay circuit generates a total delay signal. A phase detector and filter are connected to the n delay circuits for controlling the respective delays thereof so that the total delay signal locks in relation to the input clock, such as to its period. In addition, the adjustable phase clock preferably further permits control of the output based upon selecting one of the n delayed signals having a corresponding adjusted phase delay relative to the input clock signal. Of course, multiple ones of the n delayed signals can also be selected. The adjustable phase clock may be used in a line locking application and an adjustable frequency clock circuit.

Abstract: A linear interpolator and decimating FIR filter with constant coefficients may be used in various configurations to scale a still or moving color video image horizontally (changing the number of pixels per row) or vertically (changing the number of pixels per column). For downscaling, the input pixel stream is initially upscaled with an interpolator by an upscaling factor of between one and two chosen so that the result can be subsequently downscaled with a decimation-by-power-of-two finite impulse response (FIR) filter to provide the desired final scaling. Upscaling is a special case accomplished by means of linear interpolation. Vertical and horizontal scaling may be performed with different, independent scaling factors.

Abstract: A loop controller transmits data to and receives data from a plurality of I/O ports on a TDM serial loop by generating a plurality of frames which include a frame control field followed by a plurality of dedicated time slot fields. Each time slot field includes an inbound data control bit or bits followed by a data field followed by an outbound data control bit or bits. The I/O port inputs and outputs data in its dedicated data field as dictated by the respective data control bit. The loop controller and I/O ports monitor the data control bit to request data, indicate insertion of data, indicate receipt of the data and acknowledge the receipt indication to achieve a complete handshake. During an initialization frame, the I/O ports set themselves into primary and secondary data modes based on sensing a prior I/O port with the same dedicated time slot.