Abstract: The present invention relates to quaternary ammonium disinfecting cleaner compositions comprising a quaternary ammonium compound, an antimicrobial amine, and an anionic scale inhibitor. Beneficially, the compositions provide sanitizing efficacy without diminished performance and without scale formation when diluted with hard water. The compositions are suitable for inactivating and/or reducing infectious agents, particularly Norovirus, Adenovirus, and Polyomavirus.

Abstract: The invention relates to a turbine comprising a turbine housing defining a volute having a substantially annular outlet opening, a turbine wheel, and an adjusting ring, rotatable about the turbine axis, which is arranged in the turbine housing radially between the volute and the turbine wheel, wherein the adjusting ring comprises a flow channel between a radially outer first peripheral opening and a radially inner second peripheral opening, and wherein the outlet opening is fluidically coupled to the turbine wheel by the flow channel. The outlet opening and the first peripheral opening have a path, variable in the axial direction, so that during a rotation of the adjusting ring, the outlet opening and the first peripheral opening are adjusted relative to each other in such a way that an overflow cross section between the outlet opening and the first peripheral opening is variably changeable.

Abstract: Embodiments of the present disclosure describe a call recording system and a call recording method for automatically recording, i.e. storing, a call candidate when an active call is detected. The call recording system comprises a sound receiver to receive sound data and to convert sound data to audio representations of sound, a buffer to buffer the audio representations of sound for a predetermined time duration, a call candidate determination unit to determine if the buffered audio representations comprise a call candidate, a call analyzer to analyze the call candidate, wherein the call analyzer determines if the call candidate is a call to be stored, and a storage to store the call candidate as a call. Hence, a reliable system can be provided for automatically storing a call.

Abstract: Embodiments of the present disclosure describe a call recording system and a call recording method for automatically recording, i.e. storing, a call candidate when an active call is detected. The call recording system comprises a sound receiver to receive sound data and to convert sound data to audio representations of sound, a buffer to buffer the audio representations of sound for a predetermined time duration, a call candidate determination unit to determine if the buffered audio representations comprise a call candidate, a call analyzer to analyze the call candidate, wherein the call analyzer determines if the call candidate is a call to be stored, and a storage to store the call candidate as a call. Hence, a reliable system can be provided for automatically storing a call.

Abstract: The invention relates to a turbine comprising a turbine housing defining a volute having a substantially annular outlet opening, a turbine wheel, and an adjusting ring, rotatable about the turbine axis, which is arranged in the turbine housing radially between the volute and the turbine wheel, wherein the adjusting ring comprises a flow channel between a radially outer first peripheral opening and a radially inner second peripheral opening, and wherein the outlet opening is fluidically coupled to the turbine wheel by the flow channel. The outlet opening and the first peripheral opening have a path, variable in the axial direction, so that during a rotation of the adjusting ring, the outlet opening and the first peripheral opening are adjusted relative to each other in such a way that an overflow cross section between the outlet opening and the first peripheral opening is variably changeable.

Abstract: A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor body includes a load current component having a load current transistor area and a sensor component having a sensor transistor area. The load current transistor area and the sensor transistor area share a same transistor unit construction. The load current transistor area includes first and second transistor area parts, and the sensor transistor area includes a third transistor area part. The first and the third transistor area parts differ from the second transistor area part between the first and the third transistor area parts by a load current transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and second transistor area parts by the load current transistor area element being absent in the second transistor area part.

Abstract: A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor body includes a load current component having a load current transistor area and a sensor component having a sensor transistor area. The load current transistor area and the sensor transistor area share a same transistor unit construction. The load current transistor area includes first and second transistor area parts, and the sensor transistor area includes a third transistor area part. The first and the third transistor area parts differ from the second transistor area part between the first and the third transistor area parts by a load current transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and second transistor area parts by the load current transistor area element being absent in the second transistor area part.

Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor body includes a load current component having a load current transistor area and a sensor component including a sensor transistor area. The sensor transistor area has first and third transistor area parts differing from a second transistor area part between the first and third transistor area parts by a sensor transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and third transistor area parts by the sensor transistor area element being absent in the second transistor area part.

Abstract: A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: By thermal oxidation a field oxide layer is formed that lines first and second trenches that extend from a main surface into a semiconductor layer. After the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells are formed in the first and second trenches. A protection cover including a silicon nitride layer is formed that covers a cell area with the first and second trenches. With the protection cover covering the cell area, planar gate electrodes of lateral transistors are formed in a support area of the semiconductor layer.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

Abstract: By thermal oxidation a field oxide layer is formed that lines first and second trenches that extend from a main surface into a semiconductor layer. After the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells are formed in the first and second trenches. A protection cover including a silicon nitride layer is formed that covers a cell area with the first and second trenches. With the protection cover covering the cell area, planar gate electrodes of lateral transistors are formed in a support area of the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor body includes a load current component having a load current transistor area and a sensor component including a sensor transistor area. The sensor transistor area has first and third transistor area parts differing from a second transistor area part between the first and third transistor area parts by a sensor transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and third transistor area parts by the sensor transistor area element being absent in the second transistor area part.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.

Abstract: A system for annotation-based access control stores a network of interconnected data entities including Person, Resource and Policy entities, each Resource entity designated as being owned by a Person entity. The system enables a user to: define Annotations and to associate the Annotations with stored entities, each Annotation comprising terms defining the sharing of a Resource with Person entities; define Policies having associated Annotation(s); define Actions for each Policy, an action being performed on a Resource; and assign a Policy including an Annotation referring to a Person, a Person Annotation, to selected Resources. The system responds to a request from a user associated with a Person entity to perform an Action on a Resource if the Person satisfies Policies assigned to the Resource i.e. if a Resource is assigned a Policy having a Person Annotation and the Person entity has an Annotation corresponding to the Person Annotation.