Patents by Inventor Stefan Drexl

Stefan Drexl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method
    Patent number: 7968416
    Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: June 28, 2011
    Assignee: Infineon Technologies AG
    Inventors: Thomas Böttner, Stefan Drexl, Thomas Huttner, Martin Seck
  • Integrated connection arrangements
    Patent number: 7964494
    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: June 21, 2011
    Assignee: Infineon Technologies AG
    Inventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck
  • Integrated connection arrangements
    Patent number: 7619309
    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: November 17, 2009
    Assignee: Infineon Technologies AG
    Inventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Kôrner, Andrea Mitchell, Markus Schwerd, Martin Seck
  • Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method
    Patent number: 7592648
    Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: September 22, 2009
    Assignee: Infineon Technologies AG
    Inventors: Thomas Böttner, Stefan Drexl, Thomas Huttner, Martin Seck
  • Integrated connection arrangements
    Publication number: 20060192289
    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
    Type: Application
    Filed: February 9, 2006
    Publication date: August 31, 2006
    Inventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Korner, Andrea Mitchell, Markus Schwerd, Martin Seck
  • Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method
    Publication number: 20060131694
    Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.
    Type: Application
    Filed: December 6, 2005
    Publication date: June 22, 2006
    Inventors: Thomas Bottner, Stefan Drexl, Thomas Huttner, Martin Seck
  • Integrated circuit arrangement having PNP and NPN bipolar transistors, and fabrication method
    Patent number: 7038255
    Abstract: An explanation is given of, inter alia, an integrated circuit arrangement (100) containing an npn transistor (102) and a pnp transistor (104). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout (142) for an edge terminal region (120) and if the edge terminal region (120) has a part near the substrate which is arranged in the cutout (142) and a part remote from the substrate which is arranged outside the cutout (142) and overlaps the base terminal region (139).
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: May 2, 2006
    Assignee: Infineon Technologies AG
    Inventors: Thomas Böttner, Stefan Drexl, Thomas Huttner, Martin Seck
  • Integrated circuit arrangement having PNP and NPN bipolar transistors, and fabrication method
    Publication number: 20050029624
    Abstract: An explanation is given of, inter alia, an integrated circuit arrangement (100) containing an npn transistor (102) and a pnp transistor (104). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout (142) for an edge terminal region (120) and if the edge terminal region (120) has a part near the substrate which is arranged in the cutout (142) and a part remote from the substrate which is arranged outside the cutout (142) and overlaps the base terminal region (139).
    Type: Application
    Filed: June 21, 2004
    Publication date: February 10, 2005
    Inventors: Thomas Bottner, Stefan Drexl, Thomas Huttner, Martin Seck