Patents by Inventor Stefan Gernhardt
Stefan Gernhardt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7378700Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.Type: GrantFiled: March 9, 2006Date of Patent: May 27, 2008Assignee: Infineon Technologies AGInventors: Jingyu Lian, Nicolas Nagel, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, Uwe Wellhausen
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Patent number: 7316980Abstract: Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.Type: GrantFiled: October 2, 2003Date of Patent: January 8, 2008Assignee: Infineon Technologies AGInventors: Haoren Zhuang, Ulrich Egger, Rainer Bruchhaus, Karl Hornik, Jenny Lian, Stefan Gernhardt
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Patent number: 7101785Abstract: A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material in the contact hole, and filling the contact hole with a conductive material. A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids in an existing barrier layer caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.Type: GrantFiled: July 22, 2003Date of Patent: September 5, 2006Assignee: Infineon Technologies AGInventors: Andreas Hilliger, Stefan Gernhardt, Uwe Wellhausen, Karl Hornik
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Publication number: 20060151819Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.Type: ApplicationFiled: March 9, 2006Publication date: July 13, 2006Inventors: Jingyu Lian, Nicolas Nagel, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, Uwe Wellhausen
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Patent number: 7061035Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.Type: GrantFiled: October 1, 2003Date of Patent: June 13, 2006Assignee: Infineon Technologies AGInventors: Jingyu Lian, Nicolas Nagel, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, Uwe Wellhausen
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Patent number: 7001780Abstract: A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.Type: GrantFiled: August 6, 2003Date of Patent: February 21, 2006Assignees: Infineon Technologies AG, Kabushiki Kaisha ToshibaInventors: Haoren Zhuang, Ulrich Egger, Jingyu Lian, Stefan Gernhardt, Hiroyuki Kanaya
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Patent number: 6946735Abstract: The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.Type: GrantFiled: November 29, 2002Date of Patent: September 20, 2005Assignee: Infineon AGInventors: Stefan Gernhardt, Jenny Lian, Andreas Hilliger, Rainer Bruchhaus, Uwe Wellhausen, Nicolas Nagel
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Patent number: 6940111Abstract: Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.Type: GrantFiled: November 29, 2002Date of Patent: September 6, 2005Assignee: Infineon Technologies AktiengesellschaftInventors: Rainer Bruchhaus, Uwe Wellhausen, Nicolas Nagel, Stefan Gernhardt
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Publication number: 20050082583Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.Type: ApplicationFiled: October 1, 2003Publication date: April 21, 2005Inventors: Jingyu Lian, Nicolas Nagel, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, Uwe Wellhausen
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Publication number: 20050074979Abstract: Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.Type: ApplicationFiled: October 2, 2003Publication date: April 7, 2005Inventors: Haoren Zhuang, Ulrich Egger, Rainer Bruchhaus, Karl Hornik, Jenny Lian, Stefan Gernhardt
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Publication number: 20050070030Abstract: A device and method for fabricating a device comprises forming a substrate and forming a contact plug through the substrate. A first electrode is formed on the substrate and a dielectric layer is formed on the first electrode. A second electrode is formed on the ferroelectric layer and an interlayer dielectric layer is applied to the second electrode and exposed surfaces of the first electrode and the ferroelectric layer. The interlayer dielectric layer is subjected to a chemical mechanical polishing process to expose a surface of the second electrode and a metal layer is deposited onto the polished interlayer dielectric layer and the exposed surface of the second electrode. The metal layer is then etched to provide an interconnection pattern to the second electrode.Type: ApplicationFiled: September 26, 2003Publication date: March 31, 2005Inventors: Stefan Gernhardt, Haoren Zhuang, Ulrich Egger
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Publication number: 20050029563Abstract: A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.Type: ApplicationFiled: August 6, 2003Publication date: February 10, 2005Applicants: Infineon Technologies AG, Kabushiki Kaisha ToshibaInventors: Haoren Zhuang, Ulrich Egger, Jingyu Lian, Stefan Gernhardt, Hiroyuki Kanaya
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Publication number: 20050020054Abstract: A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material in the contact hole, and filling the contact hole with a conductive material. A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids in an existing barrier layer caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.Type: ApplicationFiled: July 22, 2003Publication date: January 27, 2005Inventors: Andreas Hilliger, Stefan Gernhardt, Uwe Wellhausen, Karl Hornik
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Publication number: 20050013091Abstract: A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.Type: ApplicationFiled: July 18, 2003Publication date: January 20, 2005Inventors: Andreas Hilliger, Jingyu Lian, Nicolas Nagel, Rainer Bruchhaus, Stefan Gernhardt, Uwe Wellhausen, Bum-Ki Moon, Karl Hornik
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Patent number: 6839220Abstract: A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.Type: GrantFiled: July 18, 2003Date of Patent: January 4, 2005Assignee: Infineon Technologies AGInventors: Andreas Hilliger, Jingyu Lian, Nicolas Nagel, Rainer Bruchhaus, Stefan Gernhardt, Uwe Wellhausen, Bum-Ki Moon, Karl Hornik
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Patent number: 6815234Abstract: A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.Type: GrantFiled: December 31, 2002Date of Patent: November 9, 2004Assignee: Infineon Technologies AktiengesellschaftInventors: Uwe Wellhausen, Stefan Gernhardt, Rainer Bruchhaus, Andreás Hilliger, Jing Yu Lian, Nicolas Nagel
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Publication number: 20040201049Abstract: An electrode 1 of a ferrocapacitor formed by an etching process is treated by oxygen implantation to reduce the size of crystal domains 15 in side regions 11 of the electrode 1. Subsequently a cover layer 3 is deposited over the side wall of the electrode to protect the ferrocapacitor in subsequent process steps. Later in the fabrication process the ferrocapacitor is subject to heat treatments, but due to the reduced size of the crystal domains 15 the growth of the crystal domains in the side regions 11 of the electrode is more homogenous, and causes reduced stresses in the cover layer 3, leading to a reduced risk of the cover layer 3 failing to protect the ferrocapacitor.Type: ApplicationFiled: April 11, 2003Publication date: October 14, 2004Inventors: Stefan Gernhardt, Jingyu Lian, Rainer Bruchhaus, Andreas Hilliger, Nicolas Nagel, Uwe Wellhausen
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Publication number: 20040163233Abstract: A fabrication process for ferroelectric capacitors includes forming openings 23, 30, in the device, into which electrically conductive material 28, 37 can be inserted to form electrical connections within the device. The surface of each opening is coated with a layer 24, 34 of getter material which absorbs contaminants 25, 31, 33 formed during the opening process. This means that in subsequent processing steps the contaminants do not vagabond towards the ferroelectric layers 7 of the device where they might otherwise cause damage, for example during a subsequent crystallisation stage.Type: ApplicationFiled: February 26, 2003Publication date: August 26, 2004Inventors: Stefan Gernhardt, Osamu Hidaka, Jenny Lian, Rainer Bruchhaus, Andreas Hilliger, Nicolas Nagel
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Publication number: 20040124452Abstract: A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Uwe Wellhausen, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, JingYu Lian, Nicolas Nagel
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Publication number: 20040104754Abstract: Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.Type: ApplicationFiled: November 29, 2002Publication date: June 3, 2004Inventors: Rainer Bruchhaus, Uwe Wellhausen, Nicolas Nagel, Stefan Gernhardt