Abstract: A digital signal processor that is used for echo cancellation computations is disclosed, which includes parallel multiplier/adders, an input signal sample memory, and a plurality of accumulators for temporarily storing the results of the computations performed. Consequently, not all of the computational results have to be saved in an external data memory, which minimizes data transfer bottlenecks and significantly increases the computational efficiency of the digital signal processor. The adaptive filter coefficient updates can thereby be computed much faster, and the adaptive filter coefficients can be copied much faster from one filter to the other. The computational complexity of the digital signal processor is significantly less than that of prior digital signal processors.