Abstract: A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrically isolating surface layer, preferably comprising a nitride layer. A base region in the active region is defined by a well-defined opening, which is lithographically produced, in the electrically isolating surface layer. For a bipolar lateral transistor of type PNP, which instead has emitter and collector regions surrounded by such thick field oxide areas, the emitter and collector regions can in the corresponding way be defined by a lithographically defined opening in an electrically isolating surface layer. Owing to the well defined openings the base-collector capacitance and the emitter-collector capacitance respectively can be reduced in these cases, what results in better high frequency characteristics of the transistors.

Abstract: A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrically isolating surface layer, preferably comprising a nitride layer. A base region in the active region is defined by a well-defined opening, which is lithographically produced, in the electrically isolating surface layer. For a bipolar lateral transistor of type PNP, which instead has emitter and collector regions surrounded by such thick field oxide areas, the emitter and collector regions can in the corresponding way be defined by a lithographically defined opening in an electrically isolating surface layer. Owing to the well defined openings the base-collector capacitance and the emitter-collector capacitance respectively can be reduced in these cases, what results in better high frequency characteristics of the transistors.

Abstract: The present invention relates to a method for, in the manufacturing of an integrated circuit, producing a capacitor with metallic conducting electrodes and to the capacitor itself and to the integrated circuit, which preferably are intended for high-frequency applications. According to the invention, a lower electrode (17,63,67) is produced through depositing a first metal layer (15) onto a layer structure (11) comprising lowermost a substrate and uppermost an insulating layer (13). An insulating layer (19) is deposited over the first metal layer (15), whereafter an electrical connection (25) to the lower electrode (17,63,67) is produced by etching a via hole (21) through the insulating layer (19), which via hole (21) is plugged. Thereafter the first metal layer (15) is uncovered within a predetermined area (33), whereafter a dielectric layer (35) is deposited, patterned and etched in such a way that it overlaps (39) a portion of the second insulating layer (19).

Abstract: The present invention relates to a method for, in the manufacturing of an integrated circuit, producing a capacitor with metallic conducting electrodes and to the capacitor itself and to the integrated circuit, which preferably are intended for high-frequency applications. According to the invention, a lower electrode (17,63,67) is produced through depositing a first metal layer (15) onto a layer structure (11) comprising lowermost a substrate and uppermost an insulating layer (13). An insulating layer (19) is deposited over the first metal layer (15), whereafter an electrical connection (25) to the lower electrode (17,63,67) is produced by etching a via hole (21) through said insulating layer (19), which via hole (21) is plugged. There-after the first metal layer (15) is uncovered within a predetermined area (33), whereafter a dielectric layer (35) is deposited, patterned and etched in such a way that it overlaps (39) said predetermined area (33).