Patents by Inventor Stefanie R. Chiras
Stefanie R. Chiras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9081606Abstract: A processor includes a processor core, a cache, and a tracker. The processor core is configured to execute persistent write instructions and receive notifications of completed persistent write instructions. The tracker is configured to track the completion state of a persistent write instruction.Type: GrantFiled: November 13, 2012Date of Patent: July 14, 2015Assignee: International Business Machines CorporationInventors: Gary D. Carpenter, Stefanie R. Chiras, Alexandre P. Ferreira, Jente B. Kuang, Karthick Rajamani, Freeman L. Rawson, III
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Patent number: 8897062Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: GrantFiled: June 1, 2011Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Publication number: 20140136786Abstract: A processor includes a processor core, a cache, and a tracker. The processor core is configured to execute persistent write instructions and receive notifications of completed persistent write instructions. The tracker is configured to track the completion state of a persistent write instruction.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gary D. Carpenter, Stefanie R. Chiras, Alexandre P. Ferreira, Jente B. Kuang, Karthick Rajamani, Freeman L. Rawson, III
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Patent number: 8166368Abstract: A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol.Type: GrantFiled: February 24, 2009Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Luis A. Lastras-Montano, John P. Karidis, Stefanie R. Chiras, Mayank Sharma, Thomas Mittelholzer, Michele M. Franceschini
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Publication number: 20110228600Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Patent number: 8023345Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: GrantFiled: February 24, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Patent number: 7820559Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: June 23, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Publication number: 20100218071Abstract: A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an iterative write process of at least one write and one read to the memory location. The iterative write process includes determining if the symbol was successfully written to the memory location and exiting the iterative write process in response to the symbol being successfully written to the memory location. The iterative write process also includes determining if a halt condition has been met and exiting the iterative write process if the halt condition has been met. Once the iterative write process has been exited, the memory location may be identified as a candidate for being written with a special symbol.Type: ApplicationFiled: February 24, 2009Publication date: August 26, 2010Applicant: International Business Machines CorporationInventors: Luis A. Lastras-Montano, John P. Karidis, Stefanie R. Chiras, Mayank Sharma, Thomas Mittelholzer, Michele M. Franceschini
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Publication number: 20100214829Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: ApplicationFiled: February 24, 2009Publication date: August 26, 2010Applicant: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Patent number: 7495338Abstract: A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer.Type: GrantFiled: March 16, 2006Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Michael Lane, Stefanie R. Chiras, Terry A. Spooner, Robert Rosenberg, Daniel C. Edelstein
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Publication number: 20080254643Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: June 23, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Darren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Patent number: 7402532Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: August 4, 2006Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Derren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Patent number: 7217655Abstract: A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.Type: GrantFiled: February 2, 2005Date of Patent: May 15, 2007Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Stefanie R. Chiras, Emanuel I. Cooper, Hariklia Deligianni, Andrew J. Kellock, Judith M. Rubino, Roger Y. Tsai
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Patent number: 7193323Abstract: A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.Type: GrantFiled: November 18, 2003Date of Patent: March 20, 2007Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Stefanie R. Chiras, Emanuel Cooper, Hariklia Deligianni, Andrew J. Kellock, Judith M. Rubino, Roger Y. Tsai
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Patent number: 7119018Abstract: A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer.Type: GrantFiled: July 9, 2004Date of Patent: October 10, 2006Assignee: International Buisness Machines CorporationInventors: Michael W. Lane, Stefanie R. Chiras, Terry A. Spooner, Robert Rosenberg, Daniel C. Edelstein
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Patent number: 7102232Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: April 19, 2004Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Derren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang