Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Abstract: A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.

Abstract: A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.

Abstract: A threaded connection design having a double ellipse in the thread root for reducing stress fatigue is illustrated in this disclosure. The root groove includes a first portion comprising a first elliptical surface being part of a first ellipse. The root groove further includes a second portion comprising a second elliptical surface, being part of a second ellipse, and the second elliptical surface being joined tangentially at a first end to the first elliptical surface at a junction point that defines the bottom of the root groove. The second elliptical surface is joined tangentially at a second end to the load flank.

Abstract: A threaded connection design having a double ellipse in the thread root for reducing stress fatigue is illustrated in this disclosure. The root groove includes a first portion comprising a first elliptical surface being part of a first ellipse. The root groove further includes a second portion comprising a second elliptical surface, being part of a second ellipse, and the second elliptical surface being joined tangentially at a first end to the first elliptical surface at a junction point that defines the bottom of the root groove. The second elliptical surface is joined tangentially at a second end to the load flank.

Abstract: A threaded connection design having a double ellipse in the thread root for reducing stress fatigue is illustrated in this disclosure. The root groove includes a first portion comprising a first elliptical surface being part of a first ellipse. The root groove further includes a second portion comprising a second elliptical surface, being part of a second ellipse, and the second elliptical surface being joined tangentially at a first end to the first elliptical surface at a junction point that defines the bottom of the root groove. The second elliptical surface is joined tangentially at a second end to the load flank.

Abstract: A threaded connection design having a double ellipse in the thread root for reducing stress fatigue is illustrated in this disclosure. The root groove includes a first portion comprising a first elliptical surface being part of a first ellipse. The root groove further includes a second portion comprising a second elliptical surface, being part of a second ellipse, and the second elliptical surface being joined tangentially at a first end to the first elliptical surface at a junction point that defines the bottom of the root groove. The second elliptical surface is joined tangentially at a second end to the load flank.

Abstract: An oscillator system may include an oscillator block having a plurality of inputs and outputting a clock signal, a frequency divider block receiving the clock signal and outputting a divided clock signal, a tuning block receiving the divided clock signal and outputting a comparison signal, and a control block coupled to the tuning block. The control block may receive the comparison signal. The control block may include a configuration block for producing a plurality of outputs for the corresponding inputs of the oscillator block, and an Up/Down counter having outputs applied to the configuration block.

Abstract: An oscillator system may include an oscillator block having a plurality of inputs and outputting a clock signal, a frequency divider block receiving the clock signal and outputting a divided clock signal, a tuning block receiving the divided clock signal and outputting a comparison signal, and a control block coupled to the tuning block. The control block may receive the comparison signal. The control block may include a configuration block for producing a plurality of outputs for the corresponding inputs of the oscillator block, and an Up/Down counter having outputs applied to the configuration block.