Abstract: Method for the estimation of the heart-rate using photoplethysmography on a body organ, for example a wrist of a user, comprising acquiring optically from said body organ a heart beat signal, acquiring an acceleration signal representative of the acceleration of said body organ, selecting data blocks of said acquired heart beat signal and acceleration signal, compensating said heart beat signal by the acceleration signal, calculating the heart rate value on the basis of said compensated heart beat signal.

Abstract: Method for the estimation of the heart-rate using photoplethysmography on a body organ, for example a wrist of a user, comprising acquiring optically from said body organ a heart beat signal, acquiring an acceleration signal representative of the acceleration of said body organ, selecting data blocks of said acquired heart beat signal and acceleration signal, compensating said heart beat signal by the acceleration signal, calculating the heart rate value on the basis of said compensated heart beat signal.

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set.

Abstract: A system and method is disclosed for efficiently executing single program multiple data (SPMD) programs in a microprocessor. A micro single instruction multiple data (SIMD) unit is located within the microprocessor. A job buffer that is coupled to the micro SIMD unit dynamically allocates tasks to the micro SIMD unit. The SPMD programs each comprise a plurality of input data streams having moderate diversification of control flows. The system executes each SPMD program once for each input data stream of the plurality of input data streams.

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set.

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set.

Abstract: An architecture for a rake receiver of a CMDA demodulator utilizes a common data path for signal processing. This common data path is shared by all channels (either physical channels or propagation paths within physical channels) to avoid redundant calculations, reduce circuit space and reduce power consumption. The sharing of the common data path for demodulation is made on a time divided manner, with each channel being given sequential access to the data path to perform all or part of a given demodulation function (for example, de-scrambling, de-spreading, de-rotating, and de-skewing accumulation).

Abstract: A demodulator in a wireless communication network for combining symbols without the need to store the received symbols in buffers for subsequent retrieval and accumulation. The demodulator includes a plurality of accumulators capable of accumulating received symbols, each symbol associated with a physical channel and a propagation path. The demodulator includes a multiplexer for routing the received symbols to an appropriate accumulator selected from the plurality of accumulators. The symbols received from different propagation paths are each routed and accumulated to an appropriate accumulator based on a physical channel of the received symbol and a value of an indicator associated with a propagation path of the received symbol.

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set.

Abstract: A system and method is disclosed for efficiently executing single program multiple data (SPMD) programs in a microprocessor. A micro single instruction multiple data (SIMD) unit is located within the microprocessor. A job buffer that is coupled to the micro SIMD unit dynamically allocates tasks to the micro SIMD unit. The SPMD programs each comprise a plurality of input data streams having moderate diversification of control flows. The system executes each SPMD program once for each input data stream of the plurality of input data streams.

Abstract: An architecture for a rake receiver of a CMDA demodulator utilizes a common data path for signal processing. This common data path is shared by all channels (either physical channels or propagation paths within physical channels) to avoid redundant calculations, reduce circuit space and reduce power consumption. The sharing of the common data path for demodulation is made on a time divided manner, with each channel being given sequential access to the data path to perform all or part of a given demodulation function (for example, de-scrambling, de-spreading, de-rotating, and de-skewing accumulation).

Abstract: A demodulator in a wireless communication network for combining symbols without the need to store the received symbols in buffers for subsequent retrieval and accumulation. The demodulator includes a plurality of accumulators capable of accumulating received symbols, each symbol associated with a physical channel and a propagation path. The demodulator includes a multiplexer for routing the received symbols to an appropriate accumulator selected from the plurality of accumulators. The symbols received from different propagation paths are each routed and accumulated to an appropriate accumulator based on a physical channel of the received symbol and a value of an indicator associated with a propagation path of the received symbol.

Abstract: The broadcast mode of the different ones set by the international standards for digital audio broadcasting (DAB) according to a coded orthogonal frequency division multiplexing scheme (COEFDM) may be automatically detected in a receiver through a detection routine. Many of the calculation modules required by the automatic mode detection system of the invention are already present in a receiver and can be exploited for performing the digital signal processing that leads to an automatic recognition of the broadcast mode of the station on which the receiver is tuned.