Patents by Inventor Stefano Giacconi

Stefano Giacconi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power and area efficient receiver equalization architecture with relaxed DFE timing constraint
    Patent number: 9276781
    Abstract: An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Mingming Xu, Stefano Giacconi
  • POWER AND AREA EFFICIENT RECEIVER EQUALIZATION ARCHITECTURE WITH RELAXED DFE TIMING CONSTRAINT
    Publication number: 20150163077
    Abstract: An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).
    Type: Application
    Filed: February 18, 2015
    Publication date: June 11, 2015
    Inventors: Mingming XU, Stefano Giacconi
  • Power and area efficient receiver equalization architecture with relaxed DFE timing constraint
    Patent number: 8976855
    Abstract: An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 10, 2015
    Assignee: Intel Corporation
    Inventors: Mingming Xu, Stefano Giacconi
  • POWER AND AREA EFFICIENT RECEIVER EQUALIZATION ARCHITECTURE WITH RELAXED DFE TIMING CONSTRAINT
    Publication number: 20140269889
    Abstract: An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Mingming Xu, Stefano Giacconi