Abstract: A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.

Abstract: The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed.

Abstract: The present disclosure relates to circuits and methods for improving the performance of plural DC-DC voltage converters.

Abstract: A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.

Abstract: In a device, a pulse modulation switching logic is provided to generate switching signals of a pulse modulator so as to generate a pulse modulated signal with a first pulse modulation control parameter and a second pulse modulation control parameter. The first pulse modulation control parameter is controlled on the basis of a first control signal, and the second pulse modulation control parameter is controlled on the basis of a second control signal. A first control loop is provided to generate the first control signal from an output signal derived from the pulse modulated signal. A second control loop is provided to generate the second control signal on the basis of the output signal. The first and second control signals are applied to concurrently control the first and second pulse modulation control parameters.

Abstract: A nonlinear converter, such as a DC-DC converter, includes a nonlinear controller configured to receive an output voltage and a current, and configured to generate a PWM signal. The PWM signal is generated based on setting the converter to a first phase associated with both buck and boost modes when a clock signal is asserted, and selecting a second phase associated with the buck mode of the converter, if a sliding function signal achieves a first predetermined relationship with respect to a buck threshold before a next clock signal is asserted, or selecting a third phase associated with the boost mode of the converter, if the sliding function signal achieves a second predetermined relationship with respect to a boost threshold before a next clock signal is asserted. The nonlinear converter may include a power stage configured to provide the output voltage and a coil current to the nonlinear controller.

Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

Abstract: In a method for reducing the dynamic range of a multicarrier transmission signal (12?) which is formed in a transmitter and is composed of two or more carriers, the various signal structure timings of the carriers are determined. A delay unit (100; D0, D1, . . . , DN-1) is then used to set a delay profile between the signal structure timings of various carriers, in such a manner that the signal structures of different carriers or substructures of them are not aligned in time with respect to one another.

Abstract: An electronic transmitter device has a puncturing device with two data outputs and/or an interleaver with two data inputs. An electronic receiver device has a de-interleaver with two data outputs and/or a depuncturing device with two data inputs.

Abstract: The present disclosure relates to circuits and methods for improving the performance of plural DC-DC voltage converters.

Abstract: The method is used for limiting the power of a transmission-end signal (xn) compiled from a plurality of differently spread-coded signals. In this context, it is assumed that the quantity of spread codes used for the differently spread-coded signals is known as code engagement information (Cch,SF,k; 80). First, correction spread codes are selected by virtue of the engagement information (Cch,SF,k; 80) being evaluated. On the basis of the selected correction codes, a spread-coded correction signal (y?n) is formed which is overlaid with the compiled signal (xn).

Abstract: A mixer circuit includes a first oscillator, a second oscillator, an up-conversion mixer, a down-conversion mixer, and a detect and control unit. The up-conversion mixer has a first input terminal coupled to the first oscillator and an output terminal. The down-conversion mixer has a first input terminal coupled to the output terminal of the up-conversion mixer and a second input terminal coupled to the second oscillator. The detect and control unit is coupled to the down-conversion mixer.

Abstract: Each burst of an OFDM signal which is transmitted, for example, on the basis of the IEEE 802.11a/g WLAN Standard contains a preamble with a sequence of ten short training signals. The DC offset is derived from the mean value of the signal over a measurement section of the training signal sequence, with a first subsection of the measurement section in time being weighted with a rising weighting function, and a last subsection of the measurement section in time being weighted with a falling weighting function. A central subsection, which is not weighted, may be located between the two. The signal is accumulated in this way over the measurement section, and the result is divided by the sum of the weights of the subsections. Using this procedure, the averaging process has better filter characteristics than the noise contribution from the actual signal.

Abstract: The device for detecting a useful signal comprises an autocorrelation unit (AK) for autocorrelating a signal (s(t)) which can contain a periodic signal, and a cross correlation unit (CK) for cross correlating the signal s(t) with a known signal (b(t)). Further, the device comprises a logic unit (VE) for logically combining outputs of the autocorrelation unit (AK) and of the cross correlation unit (CK) which outputs a combinatorial signal (d(t)) which specifies whether the useful signal has been detected.

Abstract: A mixer circuit includes a mixer having input terminals and an output terminal, to provide an output signal by mixing input signals, wherein the mixer exhibits leakage. The circuit also includes a signal generator coupled to one of the input terminals of the mixer to provide a correction signal, an up-conversion mixer coupled to the mixer to provide an up-converted signal by mixing a test signal with the output signal of the mixer, and a down-conversion mixer coupled to the up-conversion mixer to provide a down-converted signal by down-converting the up-converted signal. A signal detector is coupled to the down-conversion mixer and detects a spurious signal in the down-converted signal, the spurious signal indicating the leakage, and a control unit is coupled to the signal detector and the signal generator to control generation of the correction signal depending on the detected spurious signal to compensate the leakage.

Abstract: System and method for generating multiple local oscillator signals comprising a first-stage phase-locked loop (PLL) having an input to receive a first reference signal input and having an output to transmit a second reference signal, wherein the second reference signal is an integer or fractional multiple of the first reference signal; and a plurality of second-stage PLLs, each second-stage PLL having an input coupled to the output of the first-stage PLL and receiving the second reference signal, and each second-stage PLL having an output for transmitting a local oscillator signal, wherein each of the local oscillator signals is an integer multiple of the second reference signal.

Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

Abstract: Implementations related to systems and devices that make use of a power detector multiplexer are presented herein.

Abstract: System and method for generating multiple local oscillator signals comprising a first-stage phase-locked loop (PLL) having an input to receive a first reference signal input and having an output to transmit a second reference signal, wherein the second reference signal is an integer or fractional multiple of the first reference signal; and a plurality of second-stage PLLs, each second-stage PLL having an input coupled to the output of the first-stage PLL and receiving the second reference signal, and each second-stage PLL having an output for transmitting a local oscillator signal, wherein each of the local oscillator signals is an integer multiple of the second reference signal.

Abstract: A DC-offset correction circuit includes an analog circuit to generate a plurality of analog offset-correction signal values, each of which are assigned to a hop band. The analog circuit is coupled to a tap of an analog receiver chain and includes a first analog selector to select an analog offset-correction signal value, the selected analog offset correcting signal value being assigned to a current hop band. Further, the DC-offset correction circuit includes a combiner to combine a received signal with the selected analog offset-correction signal value and feed the analog receiver chain.