Abstract: A tamper detection system may include organic material and a tamper detection circuit embedded in the organic material. A portion of the organic material is ablated away to form an incision in the organic material. A portion of the tamper detection circuit obstructs a fragment of the ablation path. The tamper detection circuit remains intact. The incision enables a gas flow between a first side of the organic material and a second side of the organic material.

Abstract: A tamper detection system may include organic material and a tamper detection circuit embedded in the organic material. A portion of the organic material is ablated away to form an incision in the organic material. A portion of the tamper detection circuit obstructs a fragment of the ablation path. The tamper detection circuit remains intact. The incision enables a gas flow between a first side of the organic material and a second side of the organic material.

Abstract: Provided is a method for masking a sensitive signal by injecting noise into planes of a printed circuit board (PCB). The method comprises detecting, by a secondary integrated circuit (IC), a noise signal on a shared plane of a PCB that includes the secondary IC. The noise signal may be analyzed to determine the characteristics of the noise signal. A masking signal may be generated based on the characteristics. The masking signal may then be injected onto the shared plane.

Abstract: Provided is a method for masking a sensitive signal by injecting noise into planes of a printed circuit board (PCB). The method comprises detecting, by a secondary integrated circuit (IC), a noise signal on a shared plane of a PCB that includes the secondary IC. The noise signal may be analyzed to determine the characteristics of the noise signal. A masking signal may be generated based on the characteristics. The masking signal may then be injected onto the shared plane.

Abstract: A system to protect signal integrity includes a circuit board having a secure portion and a non-secure portion. The secure portion includes a protected circuit operable for storing security relevant data, and a secure portion power-supply element. The non-secure portion includes an unprotected circuit and a non-secure portion power-supply element corresponding to the secure portion power-supply element. The secure portion and the non-secure portion element are separated by an isolation gap. A coupling element bridges the isolation gap between the secure portion and the non-secure portion. The coupling element is electrically connected to the secure portion power-supply element within the secure portion and electrically connected to the non-secure portion power-supply portion.

Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.

Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.

Abstract: A system to protect signal integrity includes a circuit board having a secure portion and a non-secure portion. The secure portion includes a protected circuit operable for storing security relevant data, and a secure portion power-supply element. The non-secure portion includes an unprotected circuit and a non-secure portion power-supply element corresponding to the secure portion power-supply element. The secure portion and the non-secure portion element are separated by an isolation gap. A coupling element bridges the isolation gap between the secure portion and the non-secure portion. The coupling element is electrically connected to the secure portion power-supply element within the secure portion and electrically connected to the non-secure portion power-supply portion.

Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.

Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.

Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.

Abstract: A chip package comprising: a chip stack comprising at least one chip; and a thermal power plane comprising at least two substantially parallel dielectric layers having conductive connectors patterned therein, the at least two dielectric layers electrically connected by vias, wherein said vias are substantially perpendicular to the at least two dielectric layers, wherein each of the vias electrically connects to a connector patterned within a dielectric layer of the at least two dielectric layers at a via connection, wherein an inductor used in supplying power to the at least one chip is formed from the vias and from connectors electrically connecting via connections on each of the at least two dielectric layers.

Abstract: A computer program product for fabricating an optical assembly having stored computer readable program code including a first program to place a flexible portion of a substrate including a waveguide, the waveguide exposed at one end edge of the substrate upon a horizontally movable stage of a flip-chip bonder, a second program to vertically move a clamp through the stage opening to place the waveguide exposed end in a vertical position, a third program to vertically downwardly move a bond head containing an optical component upon the waveguide exposed substrate edge to position the optical component with the exposed waveguide, a fourth program to fixably mount the optical component to the substrate edge, and a fifth program to release the optical component from the bond head while moving the clamp vertically downward through the stage opening unbending the flexible portion of the substrate with the optical component mounted thereon.

Abstract: Embodiments provide a horizontally movable stage, with an opening, of a flip-chip bonder, a substrate including at least one flexible portion and a waveguide, the waveguide exposed at one end edge of the substrate positioned upon the stage with the end edge over the opening, a vertically upwardly movable clamp sized to penetrate the stage opening and positioned underneath the stage, a vertically downwardly movable bond head above the stage opening, an optical component positioned in the head, a glue dispenser positioned to provide glue to either a mating surface of the substrate exposed end edge or a mating surface of the optical component, and a controller connected to the stage, clamp, head and dispenser, including a control circuit for positioning the substrate waveguide exposed end edge underneath the optical component while dispensing glue for fixably bonding the mating surfaces of the optical component and the substrate exposed end edge.

Abstract: A chip package comprising: a chip stack comprising at least one chip; and a thermal power plane comprising at least two substantially parallel dielectric layers having conductive connectors patterned therein, the at least two dielectric layers electrically connected by vias, wherein said vias are substantially perpendicular to the at least two dielectric layers, wherein each of the vias electrically connects to a connector patterned within a dielectric layer of the at least two dielectric layers at a via connection, wherein an inductor used in supplying power to the at least one chip is formed from the vias and from connectors electrically connecting via connections on each of the at least two dielectric layers.

Abstract: Techniques for producing a flexible structure attached to a device. One embodiment includes the steps of providing a first substrate, providing a second substrate with a releasably attached flexible structure, providing a bonding layer on at least one of the first substrate and the flexible structure, adjoining the first and second substrate such that the flexible structure is attached at the first substrate by means of the bonding layer, and detaching the second substrate in such a way that the flexible structure remains on the first substrate.

Abstract: A method for fabricating an optical assembly by placing a flexible portion of a substrate, including a waveguide, upon a horizontally movable stage of a flip-chip bonder. Then moving a clamp through an opening in the stage to bend the flexible portion of the substrate to place the waveguide exposed end in approximately a vertical position and vertically downwardly moving a bond head containing an optical component upon the waveguide exposed substrate edge to position the optical component with the exposed waveguide and mounting the optical component to the substrate edge. Then releasing the optical component from the bond head while moving the clamp downward through the stage opening and unbending the flexible portion of the substrate with the optical component mounted thereon.