Patents by Inventor Steffen Rothenhäusser
Steffen Rothenhäusser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230350032Abstract: A time-of-flight sensor includes at least one pixel, including: a Si-based photocurrent collecting structure and a Ge-based photosensitive structure epitaxially grown on the photocurrent collecting structure, wherein the photocurrent collecting structure includes an n-doped region and a p-doped region, wherein the n-doped region is configured to conduct electrons of a photocurrent to at least one n-contact and wherein the p-doped region is configured to conduct holes of the photocurrent to at least one p-contact and wherein the conduction band in the p-doped region includes a barrier for the electrons of the photocurrent and the valence band in the n-doped region includes a barrier for the holes of the photocurrent.Type: ApplicationFiled: April 11, 2023Publication date: November 2, 2023Inventors: Hans TADDIKEN, Dirk OFFENBERG, Trinath Reddy PINNAPA, Steffen ROTHENHÄUßER
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Publication number: 20230071209Abstract: A time of flight sensor includes at least one pixel, including: an epitaxially-grown Ge-based photosensitive structure including an upper portion and a trunk portion, a Si-based photocurrent collecting structure, a dielectric material layer arranged at least between the upper portion of the photosensitive structure and the photocurrent collecting structure, wherein the trunk portion of the photosensitive structure is arranged within an aperture in the dielectric material layer, and at least one n-contact configured to collect electrons of a photocurrent and at least one p-contact configured to collect holes of the photocurrent, the at least one n-contact and p-contact arranged in the photocurrent collecting structure.Type: ApplicationFiled: August 30, 2022Publication date: March 9, 2023Inventors: Hans TADDIKEN, Dirk OFFENBERG, Trinath Reddy PINNAPA, Steffen ROTHENHAEUSSER
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Patent number: 9679963Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.Type: GrantFiled: December 15, 2015Date of Patent: June 13, 2017Assignee: INFINEON TECHNOLOGIES AGInventors: Dmitri Alex Tschumakow, Erhard Landgraf, Claus Dahl, Steffen Rothenhaeusser
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Publication number: 20160099311Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.Type: ApplicationFiled: December 15, 2015Publication date: April 7, 2016Inventors: Dmitri Alex TSCHUMAKOW, Erhard LANDGRAF, Claus DAHL, Steffen ROTHENHAEUSSER
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Patent number: 9219117Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.Type: GrantFiled: April 22, 2014Date of Patent: December 22, 2015Assignee: Infineon Technologies AGInventors: Dmitri Alex Tschumakow, Erhard Landgraf, Claus Dahl, Steffen Rothenhaeusser
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Publication number: 20150303254Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.Type: ApplicationFiled: April 22, 2014Publication date: October 22, 2015Applicant: Infineon Technologies AGInventors: Dmitri Alex Tschumakow, Erhard Landgraf, Claus Dahl, Steffen Rothenhaeusser
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Patent number: 9000597Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.Type: GrantFiled: August 5, 2013Date of Patent: April 7, 2015Assignee: Infineon Technologies AGInventors: Frank Huebinger, Steffen Rothenhaeusser, Kerstin Kaemmer
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Publication number: 20140167184Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.Type: ApplicationFiled: August 5, 2013Publication date: June 19, 2014Applicant: Infineon Technologies AGInventors: Frank Huebinger, Steffen Rothenhaeusser, Kerstin Kaemmer
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Patent number: 8501576Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.Type: GrantFiled: April 21, 2011Date of Patent: August 6, 2013Assignee: Infineon Technologies AGInventors: Frank Huebinger, Steffen Rothenhaeusser, Kerstin Kaemmer
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Publication number: 20120267728Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Inventors: Frank Huebinger, Steffen Rothenhaeusser, Kerstin Kaemmer
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Patent number: 7230877Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.Type: GrantFiled: October 10, 2000Date of Patent: June 12, 2007Assignee: Infineon Technologies AGInventors: Andreas Rusch, Steffen Rothenhäusser, Alexander Truby, Yoichi Otani, Ulrich Zimmermann