Abstract: A semiconductor integrated-circuit device comprises two processing subsystems, each comprising a respective processor, set of local peripherals, and bridge unit, all connected to a respective local bus. An electrical interconnect joins the respective bridge units. The first bridge unit comprises a task register, accessible over the first local bus, and can be configured to detect a write to the task register, and respond by sending an event signal over the interconnect to the second bridge unit. The second bridge unit can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor.

Abstract: A semiconductor integrated-circuit device comprises two processing subsystems, each comprising a respective processor, set of local peripherals, and bridge unit, all connected to a respective local bus. An electrical interconnect joins the respective bridge units. The first bridge unit comprises a task register, accessible over the first local bus, and can be configured to detect a write to the task register, and respond by sending an event signal over the interconnect to the second bridge unit. The second bridge unit can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor.

Abstract: A serial, half-duplex start/stop event detection circuit comprises a stop detection flip-flop clocked by a serial data input that takes a serial clock input as an input and generates a stop signal output indicative of a stop event. A start detection flip-flop, clocked by an inverted copy of the serial data input, takes the serial clock input as an input and generates a start signal output indicative of a start event. A first buffer flip-flop, clocked by an inverted copy of the serial clock input, takes the start signal output as an input and generates a first delayed start signal output. Similarly, a second buffer flip-flop, clocked by the serial clock input, takes the first delayed start signal output as an input and generates a second delayed start signal output. The second delayed start signal output resets at least one of said stop detection, start detection or first buffer flip-flops.

Abstract: A serial, half-duplex start/stop event detection circuit comprises a stop detection flip-flop clocked by a serial data input that takes a serial clock input as an input and generates a stop signal output indicative of a stop event. A start detection flip-flop, clocked by an inverted copy of the serial data input, takes the serial clock input as an input and generates a start signal output indicative of a start event. A first buffer flip-flop, clocked by an inverted copy of the serial clock input, takes the start signal output as an input and generates a first delayed start signal output. Similarly, a second buffer flip-flop, clocked by the serial clock input, takes the first delayed start signal output as an input and generates a second delayed start signal output. The second delayed start signal output resets at least one of said stop detection, start detection or first buffer flip-flops.