Patents by Inventor Stephan Jo Cecile Henri Theeuwen

Stephan Jo Cecile Henri Theeuwen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8502311
    Abstract: It is disclosed a semiconductor transistor, comprising a semiconductor substrate (111) in which a channel region (115) and a drain extension region (119) connected to the channel region are provided; a gate electrode (127) configured to provide an electric field for influencing the channel region; a first electrically conductive shield element (131) extending in a horizontal direction (103) parallel to a main surface of the semiconductor substrate and being arranged beside the gate electrode spaced apart from the drain extension region in a vertical direction (105) perpendicular to the horizontal direction; and a second electrically conductive shield element (133) arranged spaced apart from the first shield element in the vertical direction, wherein the gate electrode protrudes over the first shield element in the vertical direction.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: August 6, 2013
    Assignee: NXP B.V.
    Inventor: Stephan Jo Cecile Henri Theeuwen
  • Patent number: 8450802
    Abstract: Laterally diffused metal oxide semiconductor transistor for a radio frequency-power: amplifier comprising a drain finger (25,27) which drain finger is connected to a stack of one or more metal interconnect layers, (123,61,59,125) wherein a metal interconnect layer (123) of said stack is connected to a drain region (25) on the substrate, wherein said stack comprises a field plate (123, 125, 121) adapted to reduce the maximum magnitude of the electric field between the drain and the substrate and overlying the tip of said drain finger.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: May 28, 2013
    Assignee: NXP B.V.
    Inventors: Johannes Adrianus Maria De Boet, Henk Jan Peuscher, Paul Bron, Stephan Jo Cecile Henri Theeuwen
  • Patent number: 8357979
    Abstract: An electronic device comprising a field-effect transistor having an inter digitated structure suitable for high-frequency power applications, and having multiple threshold voltages that are provided in different regions of each a segment of the interdigitated structure. This leads to a dramatic improvement in linearity over a large power range in the back-off region under class AB signal operation.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: January 22, 2013
    Assignee: NXP B.V.
    Inventors: Thomas Christian Roedle, Hendrikus Ferdinand Franciscus Jos, Stephan Jo Cecile Henri Theeuwen, Petra Christina Anna Hammes, Radjindrepersad Gajadharsing
  • Publication number: 20110266619
    Abstract: It is disclosed a semiconductor transistor, comprising a semiconductor substrate (111) in which a channel region (115) and a drain extension region (119) connected to the channel region are provided; a gate electrode (127) configured to provide an electric field for influencing the channel region; a first electrically conductive shield element (131) extending in a horizontal direction (103) parallel to a main surface of the semiconductor substrate and being arranged beside the gate electrode spaced apart from the drain extension region in a vertical direction (105) perpendicular to the horizontal direction; and a second electrically conductive shield element (133) arranged spaced apart from the first shield element in the vertical direction, wherein the gate electrode protrudes over the first shield element in the vertical direction.
    Type: Application
    Filed: April 25, 2011
    Publication date: November 3, 2011
    Applicant: NXP B.V.
    Inventor: Stephan Jo Cecile Henri Theeuwen
  • Publication number: 20110121389
    Abstract: Laterally diffused metal oxide semiconductor transistor for a radio frequency-power: amplifier comprising a drain finger (25,27) which drain finger is connected to a stack of one or more metal interconnect layers, (123,61,59,125) wherein a metal interconnect layer (123) of said stack is connected to a drain region (25) on the substrate, wherein said stack comprises a field plate (123, 125, 121) adapted to reduce the maximum magnitude of the electric field between the drain and the substrate and overlying the tip of said drain finger.
    Type: Application
    Filed: July 20, 2009
    Publication date: May 26, 2011
    Applicant: NXP B.V.
    Inventors: Johannes Adrianus Maria De Boet, Henk Jan Peuscher, Paul Bron, Stephan Jo Cecile Henri Theeuwen
  • Patent number: 7652316
    Abstract: The invention relates to in particular a lateral DMOST with a drain extension (8). In the known transistor a further metal strip (20) is positioned between the gate electrode contact strip and the drain contact (16) which is electrically connected with the source region contact (15). In the device proposed here, the connection between the further metal strip (20) and the source contact (15,12) comprises a capacitor (30) and the further metal strip (20) is provided with a further contact region (35) for delivering a voltage to the further metal strip (20). In this way an improved linearity is possible and the usefulness of the device is improved in particular at high power and at high frequencies. Preferably the capacitor (30) is integrated with the transistor in a single semiconductor body (1). The invention further comprises a method of operating a device (10) according to the invention.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: January 26, 2010
    Assignee: DSP Group Switzerland AG
    Inventors: Radjindrepersad Gajadharsing, Thomas Christian Roedle, Petra Christina Anna Hammes, Stephan Jo Cecile Henri Theeuwen
  • Patent number: 7521768
    Abstract: The LDMOS transistor (99) of the invention is provided with a stepped shield structure (50) and/or with a first (25) and a second (26) drain extension region having a higher dopant concentration than the second drain extension region, and being covered by the shield.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: April 21, 2009
    Assignee: NXP B.V.
    Inventors: Stephan Jo Cecile Henri Theeuwen, Freerk Van Rijs, Petra Christina Anna Hammes, Ivo Bernhard Pouwel, Hendrikus Ferdinand Franciscus Jos
  • Publication number: 20080308862
    Abstract: The MOS transistor (1) of the invention comprises a gate electrode (10), a channel region (4), a drain contact region (6) and a drain extension region (7) mutually connecting the channel region (4) and the drain contact region (6). The MOS transistor (1) further comprises a shield layer (11) which extends over the drain extension region (7) wherein the distance between the shield layer (11) and the drain extension region (7) increases in a direction from the gate electrode (10) towards the drain contact region (6). In this way the lateral breakdown voltage of the MOS transistor (1) is increased to a level at which the MOS transistor (1) may fulfill the ruggedness requirement for broadcast applications for a supply voltage higher than that used in base station applications.
    Type: Application
    Filed: December 12, 2006
    Publication date: December 18, 2008
    Applicant: NXP B.V.
    Inventors: Stephan Jo Cecile Henri Theeuwen, Johannes Adrianus Maria De Boet, Johannes Gerjan Eusebius Klappe
  • Publication number: 20080237705
    Abstract: The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2?m. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.
    Type: Application
    Filed: August 2, 2006
    Publication date: October 2, 2008
    Applicant: NXP B.V.
    Inventors: Stephan Jo Cecile Henri Theeuwen, Freerk Van Rijs, Petra C.A. Hammes