Abstract: Embodiments provide line-based feature generation for vision-based driver assistance systems and methods. For one embodiment, a feature generator includes a circular buffer and a processor coupled to an image sensor. The circular buffer receives image data from the image sensor and stores N lines at a time of an image frame captured by the image sensor. The N lines of the image frame are less than all of the lines for the image frame. The processor receives the N lines from the circular buffer and stores one or more features generated from the N lines in a memory. Iterative blocks of N lines of image data are processed to complete processing of the full image frame, and multiple frames can be processed. The generated features are analyzed by a vision processor to identify, classify, and track objects for vision-based driver assistance and related vision-based assistance actions.

Abstract: A system-on-chip (SoC) includes first and second processing circuits and a data exchange circuit such that the first processing circuit is configured to process image lines based on corresponding sets of processing attributes. The first processing circuit is further configured to continuously receive and process the image lines one after the other to generate corresponding output data, and the second processing circuit is configured to continuously receive by way of the data exchange circuit, the generated output data for processing the generated output data. The data exchange circuit is thus configured to control data flow between the first processing circuit and the second processing circuit such that the first processing circuit and the second processing circuit parallelly process corresponding data associated with same or different image lines.

Abstract: A system for processing multiple images includes an access serializer, trigger controllers, a first-in-first-out (FIFO) memory, and an image signal processing (ISP) pipeline circuit. The access serializer serializes access requests that are associated with processing of input image lines of the images. The trigger controllers decode corresponding serialized access requests to generate trigger identifiers (IDs), respectively. The FIFO memory receives a corresponding trigger ID from each trigger controller and provides the trigger IDs to the ISP pipeline circuit based on an order of reception of the trigger IDs. The ISP pipeline circuit receives the input image lines associated with the trigger IDs, and based on a corresponding set of configuration parameters associated with the input image lines, processes the input image lines in an order of reception of the trigger IDs, to generate processed image lines, respectively.

Abstract: Embodiments provide line-based feature generation for vision-based driver assistance systems and methods. For one embodiment, a feature generator includes a circular buffer and a processor coupled to an image sensor. The circular buffer receives image data from the image sensor and stores N lines at a time of an image frame captured by the image sensor. The N lines of the image frame are less than all of the lines for the image frame. The processor receives the N lines from the circular buffer and stores one or more features generated from the N lines in a memory. Iterative blocks of N lines of image data are processed to complete processing of the full image frame, and multiple frames can be processed. The generated features are analyzed by a vision processor to identify, classify, and track objects for vision-based driver assistance and related vision-based assistance actions.

Abstract: A video device is described that includes: a host processor comprising at least one input video port configured to receive a plurality of video data signals that comprise video data and embedded data from a plurality of virtual channels in a received frame; and a memory operably coupled to the host processor and configured to receive and store video data. The host processor is configured to segregate the video data from the embedded data in the received frame and process the embedded data individually.

Abstract: An electronic device is described that includes: a host processor comprising at least one input port configured to receive a plurality of data signals on a plurality of virtual channels; and a memory operably coupled to the host processor and configured to receive and store data. The host processor is configured to enable and disable individual virtual channels from the plurality of virtual channels and is configured to only store data in memory associated with enabled virtual channels, and discard data from disabled channels.

Abstract: A video device is described that includes: a host processor comprising at least one input video port configured to receive a plurality of video data signals that comprise video data and embedded data from a plurality of virtual channels in a received frame; and a memory operably coupled to the host processor and configured to receive and store video data. The host processor is configured to segregate the video data from the embedded data in the received frame and process the embedded data individually.

Abstract: An electronic device is described that includes: a host processor comprising at least one input port configured to receive a plurality of data signals on a plurality of virtual channels; and a memory operably coupled to the host processor and configured to receive and store data. The host processor is configured to enable and disable individual virtual channels from the plurality of virtual channels and is configured to only store data in memory associated with enabled virtual channels, and discard data from disabled channels.