Patents by Inventor Stephane Chevobbe

Stephane Chevobbe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240232573
    Abstract: The present disclosure relates to an electronic circuit implementing a neural network, the electronic circuit comprising: an array of processing elements (PE) implementing one or more neurons of the neural network, each processing element comprising a data processing circuit, and a local memory configured to store neuron data; and data propagation circuitry configured to perform forward or reverse lateral mixing of the neuron data by propagating, synchronously by each processing element, the neuron data to the local memory of each processing element from the local memory of one or more neighboring processing elements, wherein each of the processing elements is configured to process, during a first processing iteration, the neuron data from the one or more neighboring processing elements in order to generate updated neuron data and to store the updated neuron data in the local memory for use during a subsequent processing iteration.
    Type: Application
    Filed: December 22, 2023
    Publication date: July 11, 2024
    Inventors: Thomas DALGATY, Maria LEPECQ, Stéphane CHEVOBBE
  • Patent number: 11182170
    Abstract: A processor having a SIMD architecture, including an array of elementary processors, each elementary processor being associated with an elementary memory cell, a central controller connected to the elementary processors by an instruction bus and a status bus. The central controller transmits a sequence of instructions in a loop, each instruction including a calculation flow indicator. Each elementary processor has an instruction filter that makes it possible to reject or take into account an instruction depending on the identifier it contains. This operating mode makes it possible to emulate a MIMD processor on a SIMD architecture.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 23, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stéphane Chevobbe, Marc Duranton
  • Publication number: 20210240482
    Abstract: A processor having a SIMD architecture, including an array of elementary processors, each elementary processor being associated with an elementary memory cell, a central controller connected to the elementary processors by an instruction bus and a status bus. The central controller transmits a sequence of instructions in a loop, each instruction including a calculation flow indicator. Each elementary processor has an instruction filter that makes it possible to reject or take into account an instruction depending on the identifier it contains. This operating mode makes it possible to emulate a MIMD processor on a SIMD architecture.
    Type: Application
    Filed: June 6, 2019
    Publication date: August 5, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stéphane CHEVOBBE, Marc DURANTON
  • Patent number: 9864722
    Abstract: A communication system coupled to a data-acquisition circuit and to a data-processing circuit is provided, including at least one shift register, an addressing circuit and a multiplexer. The shift register includes a serial input for inputting and storing data in series, a serial output for outputting data in series, and parallel outputs for outputting data stored in the shift register in parallel. The addressing circuit is coupled to the shift register in order to identify the positions of stored data, and the multiplexer is coupled to the parallel outputs of the shift register in order to output the stored data to the data-processing circuit in series. Methods for communication between a data-acquisition circuit and a data-processing circuit are also provided.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 9, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Stephane Chevobbe, Marc Duranton
  • Patent number: 9542719
    Abstract: A device for decomposing images into at least three levels by wavelet transform comprises a first unit executing a first level of decomposition and a second unit executing the higher levels of decomposition by performing a sequence of processing tasks. The tasks are ordered in time by using a sequence of rows, a routing unit serving to configure the second unit when the level of decomposition associated with the processing task currently being executed changes relative to the level of decomposition associated with the processing task executed previously. The processing tasks are ordered so that any given row is associated with only one level of decomposition.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: January 10, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sebastien Courroux, Stephane Chevobbe, Mehdi Darouich, Michel Paindavoine
  • Publication number: 20150262325
    Abstract: A device for decomposing images into at least three levels by wavelet transform comprises a first unit executing a first level of decomposition and a second unit executing the higher levels of decomposition by performing a sequence of processing tasks. The tasks are ordered in time by using a sequence of rows, a routing unit serving to configure the second unit when the level of decomposition associated with the processing task currently being executed changes relative to the level of decomposition associated with the processing task executed previously. The processing tasks are ordered so that any given row is associated with only one level of decomposition.
    Type: Application
    Filed: September 24, 2013
    Publication date: September 17, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sebastien Courroux, Stephane Chevobbe, Mehdi Darouich, Michel Paindavoine
  • Publication number: 20150212970
    Abstract: The present invention relates to a communication system coupled to a data-acquisition circuit and to a data-processing circuit, including at least one shift register, an addressing circuit and a multiplexer. The shift register includes a serial input for inputting and storing data in series, a serial output for outputting data in series, and parallel outputs for outputting data stored in said shift register in parallel. The addressing circuit is coupled to the shift register in order to identify the positions of stored data, and the multiplexer is coupled to the parallel outputs of the shift register in order to output the stored data to the data-processing circuit in series. The present invention also relates to methods for communication between a data-acquisition circuit and a data-processing circuit.
    Type: Application
    Filed: December 14, 2012
    Publication date: July 30, 2015
    Inventors: Stéphane Chevobbe, Marc Duranton
  • Patent number: 8656102
    Abstract: A method for preloading into a hierarchy of memories, bitstreams representing the configuration information for a reconfigurable processing system including several processing units. The method includes an off-execution step of determining tasks that can be executed on a processing unit subsequently to the execution of a given task. The method also includes, during execution of the given task, computing a priority for each of the tasks that can be executed. The priority depends on information relating to the current execution of the given task. The method also includes, during execution of the given task, sorting the tasks that can be executed in the order of their priorities. The method also includes, during execution of the given task, preloading into the memory, bitstreams representing the information of the configurations for the execution of the tasks that can be executed, while favoring the tasks whose priority is the highest.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: February 18, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Stéphane Guyetant, Stéphane Chevobbe
  • Patent number: 8522243
    Abstract: The invention relates to a method for scheduling the processing of tasks and to the associated device, the processing of a task comprising a step for configuring resources required for executing the task and a step for executing the task on the thereby configured resources, the method comprising a selection (1) of at least one level of independent tasks to be processed in accordance with an order of precedence and a step for sorting (2) out the tasks of the level of tasks to be processed in order to define, an order of priority in the processing of the tasks, depending on the number of resources required for processing the tasks on the one hand and on a time characteristic of the tasks on the other hand.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: August 27, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Nicolas Ventroux, Stéphane Chevobbe, Frédéric Blanc, Thierry Collette
  • Publication number: 20110055480
    Abstract: A method for preloading into a hierarchy of memories, bitstreams representing the configuration information for a reconfigurable processing system including several processing units. The method includes an off-execution step of determining tasks that can be executed on a processing unit subsequently to the execution of a given task. The method also includes, during execution of the given task, computing a priority for each of the tasks that can be executed. The priority depends on information relating to the current execution of the given task. The method also includes, during execution of the given task, sorting the tasks that can be executed in the order of their priorities. The method also includes, during execution of the given task, preloading into the memory, bitstreams representing the information of the configurations for the execution of the tasks that can be executed, while favoring the tasks whose priority is the highest.
    Type: Application
    Filed: February 6, 2009
    Publication date: March 3, 2011
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stéphane Guyetant, Stéphane Chevobbe
  • Publication number: 20080263555
    Abstract: The invention relates to a method for scheduling the processing of tasks and to the associated device, the processing of a task comprising a step for configuring resources required for executing the task and a step for executing the task on the thereby configured resources, the method comprising a selection (1) of at least one level of independent tasks to be processed in accordance with an order of precedence and a step for sorting (2) out the tasks of the level of tasks to be processed in order to define, an order of priority in the processing of the tasks, depending on the number of resources required for processing the tasks on the one hand and on a time characteristic of the tasks on the other hand.
    Type: Application
    Filed: July 28, 2005
    Publication date: October 23, 2008
    Applicant: Commissariat A L'Energie Atomique
    Inventors: Nicolas Ventroux, Stephane Chevobbe, Frederic Blanc, Thierry Collette