Patents by Inventor Stephane Pinel
Stephane Pinel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150199743Abstract: Embodiments of the disclosure provide content-based recommendations for organization-to-organization trading. In certain embodiments, a flexible and scalable content-based hybrid recommendation platform can permit generation of a complementary set of dual recommendations for products and seller networks from a buying and selling perspective.Type: ApplicationFiled: January 12, 2015Publication date: July 16, 2015Inventors: Stephane Pinel, Paul David Sims, Stanley Cooper Green, Gregory Claud Easterly
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Patent number: 8605826Abstract: A receiver system and a demodulator system are configured to receive and demodulate, respectively, multi-gigabit millimeter wave signals being wirelessly transmitted in the unlicensed wireless band near 60 GHz.Type: GrantFiled: August 4, 2010Date of Patent: December 10, 2013Assignee: Georgia Tech Research CorporationInventors: Eric Juntunen, Stephane Pinel, Joy Laskar, David Yeh, Saikat Sarkar
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Patent number: 8473535Abstract: A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.Type: GrantFiled: December 3, 2008Date of Patent: June 25, 2013Assignee: Georgia Tech Research CorporationInventors: Bevin George Perumana, Arun Rachamadugu, Stephane Pinel, Joy Laskar
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Patent number: 8378874Abstract: An analog to digital converter for operating at high speeds can be implemented with a micro-comparator/sampler, an encoder, and a selector. The micro-comparator includes an input from an antenna of a receiver/transceiver system; a transistor pair; reset transistor; cascaded inverters; an inverter circuit; a buffer; and a D flip flop circuit. Depending on the number of micro-comparator/samplers placed in parallel, a number of bits can be generated. For example, 15 bits from 15 different micro-comparator/samplers can be inserted into a 15 to 4 bit encoder to generate 4 bits.Type: GrantFiled: July 31, 2008Date of Patent: February 19, 2013Assignee: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar
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Patent number: 8286328Abstract: A method of fabricating an ultra-high frequency module is disclosed. The method includes providing a top layer; drilling the top layer; milling the top layer; providing a bottom; milling the bottom layer to define a bottom layer cavity; aligning the top layer and the bottom layer; and adhering the top layer to the bottom layer. The present invention also includes an ultra-high frequency module operating at ultra-high speeds having a top layer, the top layer defining a top layer cavity; a bottom layer, the bottom layer defining a bottom layer cavity; and an adhesive adhering both the top layer to the bottom layer, wherein the top layer and the bottom layer are formed from a large area panel of a printed circuit board.Type: GrantFiled: January 4, 2011Date of Patent: October 16, 2012Inventors: Stephane Pinel, Joy Laskar
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Patent number: 8081948Abstract: An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.Type: GrantFiled: October 25, 2007Date of Patent: December 20, 2011Assignee: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar, David Yeh, Bevin George Perumana, Saikat Sarkar
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Publication number: 20110291872Abstract: An analog to digital converter for operating at high speeds can be implemented with a micro-comparator/sampler, an encoder, and a selector. The micro-comparator includes an input from an antenna of a receiver/transceiver system; a transistor pair; reset transistor; cascaded inverters; an inverter circuit; a buffer; and a D flip flop circuit. Depending on the number of micro-comparator/samplers placed in parallel, a number of bits can be generated. For example, 15 bits from 15 different micro-comparator/samplers can be inserted into a 15 to 4 bit encoder to generate 4 bits.Type: ApplicationFiled: July 31, 2008Publication date: December 1, 2011Applicant: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar
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Patent number: 8067987Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.Type: GrantFiled: October 10, 2008Date of Patent: November 29, 2011Assignee: Georgia Tech Research CorporationInventors: Padmanava Sen, Saikat Sarkar, Stephane Pinel, Joy Laskar, Francesco Barale
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Publication number: 20110207425Abstract: A receiver system and a demodulator system are configured to receive and demodulate, respectively, multi-gigabit millimeter wave signals being wirelessly transmitted in the unlicensed wireless band near 60 GHz.Type: ApplicationFiled: August 4, 2010Publication date: August 25, 2011Applicant: Georgia Tech Research CorporationInventors: Eric JUNTUNEN, Stephane PINEL, Joy LASKAR, David YEH, Saikat SARKAR
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Publication number: 20110120628Abstract: A method of fabricating an ultra-high frequency module is disclosed. The method includes providing a top layer; drilling the top layer; milling the top layer; providing a bottom; milling the bottom layer to define a bottom layer cavity; aligning the top layer and the bottom layer; and adhering the top layer to the bottom layer. The present invention also includes an ultra-high frequency module operating at ultra-high speeds having a top layer, the top layer defining a top layer cavity; a bottom layer, the bottom layer defining a bottom layer cavity; and an adhesive adhering both the top layer to the bottom layer, wherein the top layer and the bottom layer are formed from a large area panel of a printed circuit board.Type: ApplicationFiled: January 4, 2011Publication date: May 26, 2011Applicant: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar
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Patent number: 7864113Abstract: A method of fabricating an ultra-high frequency module is disclosed. The method includes providing a top layer; drilling the top layer; milling the top layer; providing a bottom; milling the bottom layer to define a bottom layer cavity; aligning the top layer and the bottom layer; and adhering the top layer to the bottom layer. The present invention also includes an ultra-high frequency module operating at ultra-high speeds having a top layer, the top layer defining a top layer cavity; a bottom layer, the bottom layer defining a bottom layer cavity; and an adhesive adhering both the top layer to the bottom layer, wherein the top layer and the bottom layer are formed from a large area panel of a printed circuit board.Type: GrantFiled: March 31, 2006Date of Patent: January 4, 2011Assignee: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar
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Publication number: 20100214026Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.Type: ApplicationFiled: October 10, 2008Publication date: August 26, 2010Applicant: Georgia Tech Research CorporationInventors: Padmanava Sen, Saikat Sarkar, Stephane Pinel, Joy Laskar, Francesco Barale
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Publication number: 20100093299Abstract: An analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits quadrature phase shift keying (QPSK) modulated using a CMOS (complementary metal-oxide semiconductor) process. Further, an analog multi-gigabit receiver and/or transceiver can be implemented for the reception and demodulation of multi-gigabits binary phase shift keying (BPSK), minimum shift keying (MSK), and/or amplitude shift keying (ASK) signal modulated in CMOS processes.Type: ApplicationFiled: October 25, 2007Publication date: April 15, 2010Applicant: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar, David Yeh, Bevin George Perumana, Saikat Sarkar
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Patent number: 7593704Abstract: The present invention describes a receiver assembly for receiving an analog signal and converting the analog signal to a digital signal. The receiver assembly is, preferably, capable of receiving a signal operating at approximately 60 GHz. The receiver assembly includes a filter, a down converter, a demodulator, a latch, a FIFO, and a logic circuit. A method of converting the 60 GHz analog signal to a digital signal is also described.Type: GrantFiled: March 31, 2006Date of Patent: September 22, 2009Assignee: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar
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Publication number: 20090140784Abstract: A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission.Type: ApplicationFiled: December 3, 2008Publication date: June 4, 2009Applicant: Georgia Tech Research CorporationInventors: Bevin George PERUMANA, Arun Rachamadugu, Stephane Pinel, Joy Laskar
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Patent number: 7489201Abstract: Disclosed is a gain boosting technique for use with millimeter-wave cascode amplifiers. The exemplary technique may be implemented using a 0.18 ?m SiGe process (FT=140 GHz). It has also been shown that the technique is effective for CMOS processes with comparable FT. An exemplary gain-enhanced cascode stage was measured to have higher than 9 dB gain with a 1-dB bandwidth above 6 GHz with a DC power consumption of 13 mW. In addition, one cascode stage without gain boosting may be cascaded with two gain-boosted cascode amplifier stages to implement a three-stage LNA. The measured stable gain is higher than 24 dB at 60 GHz with a 3-dB bandwidth of 3.1 GHz for 25 mW of DC power consumption. It is believed that this is the first 60 GHz LNA with a higher than 20 dB gain using a 0.18 ?m SiGe process.Type: GrantFiled: May 9, 2007Date of Patent: February 10, 2009Assignee: Georgia Tech Research Corp.Inventors: Saikat Sarkar, Padmanava Sen, Stephane Pinel, Joy Laskar
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Publication number: 20070273445Abstract: Disclosed is a gain boosting technique for use with millimeter-wave cascode amplifiers. The exemplary technique may be implemented using a 0.18 ?m SiGe process (FT=140 GHz). It has also been shown that the technique is effective for CMOS processes with comparable FT. An exemplary gain-enhanced cascode stage was measured to have higher than 9 dB gain with a 1-dB bandwidth above 6 GHz with a DC power consumption of 13 mW. In addition, one cascode stage without gain boosting may be cascaded with two gain-boosted cascode amplifier stages to implement a three-stage LNA. The measured stable gain is higher than 24 dB at 60 GHz with a 3-dB bandwidth of 3.1 GHz for 25 mW of DC power consumption. It is believed that this is the first 60 GHz LNA with a higher than 20 dB gain using a 0.18 ?m SiGe process.Type: ApplicationFiled: May 9, 2007Publication date: November 29, 2007Inventors: Saikat Sarkar, Padmanava Sen, Stephane Pinel, Joy Laskar
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Publication number: 20060250308Abstract: A method of fabricating an ultra-high frequency module is disclosed. The method includes providing a top layer; drilling the top layer; milling the top layer; providing a bottom; milling the bottom layer to define a bottom layer cavity; aligning the top layer and the bottom layer; and adhering the top layer to the bottom layer. The present invention also includes an ultra-high frequency module operating at ultra-high speeds having a top layer, the top layer defining a top layer cavity; a bottom layer, the bottom layer defining a bottom layer cavity; and an adhesive adhering both the top layer to the bottom layer, wherein the top layer and the bottom layer are formed from a large area panel of a printed circuit board.Type: ApplicationFiled: March 31, 2006Publication date: November 9, 2006Applicant: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar
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Publication number: 20060232469Abstract: The present invention describes a receiver assembly for receiving an analog signal and converting the analog signal to a digital signal. The receiver assembly is, preferably, capable of receiving a signal operating at approximately 60 GHz. The receiver assembly includes a filter, a down converter, a demodulator, a latch, a FIFO, and a logic circuit. A method of converting the 60 GHz analog signal to a digital signal is also described.Type: ApplicationFiled: March 31, 2006Publication date: October 19, 2006Applicant: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar
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Publication number: 20060223439Abstract: A wireless repeater assembly is described. The wireless repeater assembly includes a receiver for receiving wireless data communications, wherein the receiver includes a receiving antenna for receiving analog signals; a receiver filter adapted to enable frequencies of a predetermined range to pass onto a receiver amplifier; and the receiver amplifier for boosting a signal emitted from the receiver filter; a transmitter for transmitting wireless data communications, wherein the transmitter includes a transmitter amplifier for boosting a signal coming from the receiver; a transmitter filter adapted to enable frequencies of a predetermined range to pass onto the transmitting antenna; and a transmitting antenna for transmitting signals from the repeater assembly; and a hard wire connection between the receiver and the transmitter, wherein the receiver and the transmitter are in wired communication. The wireless repeater assembly can operate at approximately 60 GHz.Type: ApplicationFiled: March 31, 2006Publication date: October 5, 2006Applicant: Georgia Tech Research CorporationInventors: Stephane Pinel, Joy Laskar