Patents by Inventor Stephanie W. Butler
Stephanie W. Butler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100229056Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.Type: ApplicationFiled: May 20, 2010Publication date: September 9, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Cloves R. Cleavelin, Andrew Marshall, Stephanie W. Butler, Howard L. Tigelaar
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Patent number: 7793186Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.Type: GrantFiled: May 20, 2010Date of Patent: September 7, 2010Assignee: Texas Instruments IncorporatedInventors: Cloves R. Cleavelin, Andrew Marshall, Stephanie W. Butler, Howard L. Tigelaar
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Patent number: 7752518Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.Type: GrantFiled: February 13, 2008Date of Patent: July 6, 2010Assignee: Texas Instruments IncorporatedInventors: Cloves R. Cleavelin, Andrew Marshall, Stephanie W. Butler, Howard L. Tigelaar
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Patent number: 7704883Abstract: A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.Type: GrantFiled: December 22, 2006Date of Patent: April 27, 2010Assignee: Texas Instruments IncorporatedInventors: Stephanie W. Butler, Yuanning Chen
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Publication number: 20090204861Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.Type: ApplicationFiled: February 13, 2008Publication date: August 13, 2009Inventors: Cloves R. Cleavelin, Andrew Marshall, Stephanie W. Butler, Howard L. Tigelaar
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Publication number: 20080251864Abstract: A method for implementing a stacked gate, comprising forming a gate dielectric on a semiconductor body, forming a first layer of gate electrode material on the gate dielectric, forming a second layer of gate electrode material on the first layer of gate electrode material, wherein the grain size distribution of the first layer of gate electrode material is different than the grain size distribution of the second layer of gate electrode material, implanting the first and second gate electrode materials, patterning the first and the second gate electrodes and the gate dielectric, and forming source and drain regions.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Inventors: Yuanning Chen, Stephanie W. Butler, Ajith Varghese, Narendra Singh Mehta
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Publication number: 20080150045Abstract: A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.Type: ApplicationFiled: December 22, 2006Publication date: June 26, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Stephanie W. Butler, Yuanning Chen
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Patent number: 7345355Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.Type: GrantFiled: September 15, 2004Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventors: Amitabh Jain, Stephanie W. Butler
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Patent number: 6808997Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.Type: GrantFiled: March 21, 2003Date of Patent: October 26, 2004Assignee: Texas Instruments IncorporatedInventors: Amitabh Jain, Stephanie W. Butler
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Publication number: 20040185633Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.Type: ApplicationFiled: March 21, 2003Publication date: September 23, 2004Applicant: Texas Instruments IncorporatedInventors: Amitabh Jain, Stephanie W. Butler
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Patent number: 5864773Abstract: A virtual sensor based monitoring and fault detection/classification system (10) for semiconductor processing equipment (12) is provided. A plurality of equipment sensors (14) are each operable to measure a process condition and provide a signal representing the measured process condition. A plurality of filtering process units (16) are each operable to receive at least one signal from the plurality of equipment sensors (14) and to reduce data represented by the at least one signal and provide filtered data. A plurality of virtual sensors (24) are each operable to receive the filtered data. The plurality of virtual sensors (24) model states of the processing equipment (12) and a work piece in the processing equipment (12). Each virtual sensor is operable to provide an output signal representing an estimated value for the modeled state.Type: GrantFiled: November 1, 1996Date of Patent: January 26, 1999Assignee: Texas Instruments IncorporatedInventors: Gabriel G. Barna, Stephanie W. Butler, Donald A. Sofge, David A. White
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Patent number: 5503707Abstract: In accordance with one aspect of the present invention, a method is provided for predicting the endpoint time of a semiconductor process for a layer of a wafer (14). The endpoint time is the time at which a predetermined thickness of the layer occurs. A layer thickness, calculated for a first sample time, is received. It is then determined whether or not the layer thickness lies within a predetermined range. If the layer thickness does lie within the predetermined range, it is used to update a forecasted process rate. The forecasted process rate is used to predict the endpoint time. The endpoint time is used to control the semiconductor process so that the layer of wafer (14) is formed having the predetermined thickness.Type: GrantFiled: September 22, 1993Date of Patent: April 2, 1996Assignee: Texas Instruments IncorporatedInventors: Sonny Maung, Stephanie W. Butler, Steven A. Henck
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Patent number: 5458732Abstract: A plasma processing system 10 for fabricating a semiconductor wafer 24 is disclosed. The system includes a plasma processing tool 12 and an RF energy source 20 coupled to the plasma processing tool 12. An optional matching network 22 may be included between the RF energy source 20 and the plasma processing tool 12. Circuitry 18 for monitoring the RF energy to obtain a measurement characteristic is also provided. At least one transducer 14 or 16 is coupled between the plasma processing tool 12 and the circuitry 18 for monitoring the RF energy. The RF energy is typically applied at a fundamental frequency and the electrical characteristic is monitored at a second frequency different than the fundamental frequency. Also included is circuitry 19, such as a computer, for interpreting the measurement to determine a condition of the processing system 10. Other systems and methods are also disclosed.Type: GrantFiled: January 28, 1994Date of Patent: October 17, 1995Assignee: Texas Instruments IncorporatedInventors: Stephanie W. Butler, Keith J. Brankner
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Patent number: 5402367Abstract: The present invention configures a control strategy and a process model to calculate a setting of a machine. The present invention adjusts the process model in accordance with an analysis of the setting to control the machine.Type: GrantFiled: July 19, 1993Date of Patent: March 28, 1995Assignee: Texas Instruments, IncorporatedInventors: Michael F. Sullivan, Judith S. Hirsch, Stephanie W. Butler, Nicholas J. Tovell, Jerry A. Stefani, Purnendu K. Mozumder, Ulrich H. Wild, Chun-Jen J. Wang, Robert A. Hartzell
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Patent number: 5399229Abstract: A system (60) and method for monitoring, evaluating and controlling the uniformity of a semiconductor wafer fabrication process is provided for use in manufacturing integrated circuits on semiconductor wafers (40). By using in situ ellipsometry (20) in conjunction with statistical modeling methods, the spatial etch rate pattern across a semiconductor wafer (40) may be inferred as a function of the process conditions. A predicted mean etch rate may be calculated for other locations (46 and 48) on the semiconductor wafer surface (42) by using the mean etch rate measured at the selected ellipsometer site (44) and individual spatial etch rate models developed for each site (44 and 48) based on statistically designed experiments. The predicted mean etch rate at the other sites (46 and 48) is also a function of the fabrication process conditions.Type: GrantFiled: May 13, 1993Date of Patent: March 21, 1995Assignee: Texas Instruments IncorporatedInventors: Jerry A. Stefani, Stephanie W. Butler