Abstract: Bonded semiconductor device structures and device structure fabrication processes to obviate the need for SOI wafers in many device fabrication applications are disclosed. In some examples, an etch stop layer is formed in situ during fabrication of an active device structure on a bulk semiconductor wafer. The etch stop layer enables the active device structure to be separated from the bulk semiconductor wafer in a layer transfer process in which the active device structure is bonded to a handle wafer. These examples enable the production of high-performance and low-power semiconductor devices (e.g., fully or partially depleted channel transistors) while avoiding the high costs of SOI wafers. In some examples, the gate masks the etch stop layer implant in a self-aligned process to create a fully depleted channel under the gate and deeper implants in the source and drain regions without requiring a separate masking layer.

Abstract: Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer. The semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate. The exemplary method further comprises applying a treatment to the semiconductor on insulator wafer using the gate as a mask. The treatment creates a treated insulator region in the buried insulator. The exemplary method also comprises removing at least a portion of the substrate. The exemplary method also comprises, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region after removing that portion of the substrate.

Abstract: Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer. The semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate. The exemplary method further comprises applying a treatment to the semiconductor on insulator wafer using the gate as a mask. The treatment creates a treated insulator region in the buried insulator. The exemplary method also comprises removing at least a portion of the substrate. The exemplary method also comprises, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region after removing that portion of the substrate.

Abstract: Bonded semiconductor device structures and device structure fabrication processes to obviate the need for SOI wafers in many device fabrication applications are disclosed. In some examples, an etch stop layer is formed in situ during fabrication of an active device structure on a bulk semiconductor wafer. The etch stop layer enables the active device structure to be separated from the bulk semiconductor wafer in a layer transfer process in which the active device structure is bonded to a handle wafer. These examples enable the production of high-performance and low-power semiconductor devices (e.g., fully or partially depleted channel transistors) while avoiding the high costs of SOI wafers. In some examples, the gate masks the etch stop layer implant in a self-aligned process to create a fully depleted channel under the gate and deeper implants in the source and drain regions without requiring a separate masking layer.

Abstract: Bonded semiconductor device structures and device structure fabrication processes to obviate the need for SOI wafers in many device fabrication applications are disclosed. In some examples, an etch stop layer is formed in situ during fabrication of an active device structure on a bulk semiconductor wafer. The etch stop layer enables the active device structure to be separated from the bulk semiconductor wafer in a layer transfer process in which the active device structure is bonded to a handle wafer. These examples enable the production of high-performance and low-power semiconductor devices (e.g., fully or partially depleted channel transistors) while avoiding the high costs of SOI wafers. In some examples, the gate masks the etch stop layer implant in a self-aligned process to create a fully depleted channel under the gate and deeper implants in the source and drain regions without requiring a separate masking layer.

Abstract: A semiconductor structure is formed with a first wafer (e.g. a handle wafer) and a second wafer (e.g. a bulk silicon wafer) bonded together. The second wafer includes an active layer, which in some embodiments is formed before the two wafers are bonded together. A substrate is removed from the second wafer on an opposite side of the active layer from the first wafer using a SiGeC or SiGeBC layer as an etch stop. In some embodiments, the SiGeC or SiGeBC layer is formed by epitaxial growth, ion implantation or a combination of epitaxial growth and ion implantation.

Abstract: An semiconductor on insulator wafer has an insulator layer between a substrate layer and a semiconductor layer. A first active layer is formed in and on the semiconductor layer. A second active layer is formed in and on the substrate layer. In some embodiments, a handle wafer is bonded to the semiconductor on insulator wafer, and the substrate layer is thinned before forming the second active layer. In some embodiments, a third active layer may be formed in the substrate of the handle wafer. In some embodiments, the first and second active layers include a MEMS device in one of these layers and a CMOS device in the other.

Abstract: Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer. The semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate. The exemplary method further comprises applying a treatment to the semiconductor on insulator wafer using the gate as a mask. The treatment creates a treated insulator region in the buried insulator. The exemplary method also comprises removing at least a portion of the substrate. The exemplary method also comprises, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region after removing that portion of the substrate.

Abstract: A semiconductor structure is formed with a first wafer (e.g. a handle wafer) and a second wafer (e.g. a bulk silicon wafer) bonded together. The second wafer includes an active layer, which in some embodiments is formed before the two wafers are bonded together. A substrate is removed from the second wafer on an opposite side of the active layer from the first wafer using a SiGeC or SiGeBC layer as an etch stop. In some embodiments, the SiGeC or SiGeBC layer is formed by epitaxial growth, ion implantation or a combination of epitaxial growth and ion implantation.

Abstract: A semiconductor structure is formed with a first wafer (e.g. a handle wafer) and a second wafer (e.g. a bulk silicon wafer) bonded together. The second wafer includes an active layer, which in some embodiments is formed before the two wafers are bonded together. A substrate is removed from the second wafer on an opposite side of the active layer from the first wafer using a SiGeC layer as an etch stop. In some embodiments, the SiGeC layer is then removed; but in some other embodiments, it remains as a strain-inducing layer.

Abstract: The fishing rod and reel carrying case is designed to house a fully assembled rod and reel for transport and temporary storage thereof. The case is of an elongate configuration and incorporates a zipper or the like for closing and opening the case. The case incorporates handles to enhance transport thereof. The case is fabricated from a composite material that provides protection from damage for the encased rod and reel, and also provides for buoyancy should the case fall into the water.