Abstract: A digital integrated circuit provided with a dual latch clocked LSSD that includes a master latch coupled to a slave latch such that it operates in at least three operational modes. Preferably the three modes of the dual latch clocked LSSD include a functional mode, a capture mode, and a shift mode. In the functional mode, the dual latch clocked LSSD operates as an edge-triggered flip-flop storage element. In the capture mode, the dual latch clocked LSSD operates as a level sensitive latch storage element controlled by the system clock, one of two scan clock signals, and, preferably, by a test mode input signal. In the shift mode, the dual latch clocked LSSD again operates as a level sensitive latch storage element, but is controlled by a pair of shift clocks. By separating the capture mode from the functional mode, the dual latch clocked LSSD is exceptionally resistant to skew problems in both the capture and the shift modes.

Abstract: A digital integrated circuit provided with a dual latch clocked LSSD that includes a master latch coupled to a slave latch such that it operates in at least three operational modes. Preferably the three modes of the dual latch clocked LSSD include a functional mode, a capture mode, and a shift mode. In the functional mode, the dual latch clocked LSSD operates as an edge-triggered flip-flop storage element. In the capture mode, the dual latch clocked LSSD operates as a level sensitive latch storage element controlled by the system clock, one of two scan clock signals, and, preferably, by a test mode input signal. In the shift mode, the dual latch clocked LSSD again operates as a level sensitive latch storage element, but is controlled by a pair of shift clocks. By separating the capture mode from the functional mode, the dual latch clocked LSSD is exceptionally resistant to skew problems in both the capture and the shift modes.