Patents by Inventor Stephen Arlon Meisner
Stephen Arlon Meisner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230134102Abstract: A photo alignment structure is provided that includes a wafer having scribe lines defined therein in a top planar surface of the wafer. An alignment structure is disposed on a top planar surface of the wafer longitudinally aligned with a portion of selected scribe lines, where the alignment structure is comprised of metal layers. A slot is defined along a longitudinal axis of the alignment structure in at least one of the metal layers.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Stephen Arlon Meisner, James Thomas Hallowell, Michael Todd Wyant
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Publication number: 20220069067Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.Type: ApplicationFiled: October 13, 2021Publication date: March 3, 2022Inventors: Poornika FERNANDES, David Matthew CURRAN, Stephen Arlon MEISNER, Bhaskar SRINIVASAN, Guruvayurappan S. MATHUR, Scott William JESSEN, Shih Chang CHANG, Russell Duane FIELDS, Thomas Terrance LYNCH
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Publication number: 20210398910Abstract: An integrated circuit includes a circuit area, and first and second scribe line portions. The first scribe line portion borders a first side of the circuit area, and the second scribe line portion borders a different second side of the circuit area. A plurality of dummy metal structures are located in the first and second scribe line portions, each of the dummy metal structures being located about at a lattice point of a same two-dimensional grid.Type: ApplicationFiled: July 15, 2021Publication date: December 23, 2021Inventors: Adrian SALINAS, William Keith McDONALD, Scott Alexander JOHANNESMEYER, Robert Paul LUCKIN, Stephen Arlon MEISNER
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Patent number: 11094644Abstract: In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.Type: GrantFiled: November 11, 2019Date of Patent: August 17, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Adrian Salinas, William Keith McDonald, Scott Alexander Johannesmeyer, Robert Paul Luckin, Stephen Arlon Meisner
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Publication number: 20210104468Abstract: In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.Type: ApplicationFiled: November 11, 2019Publication date: April 8, 2021Inventors: Adrian SALINAS, William Keith McDONALD, Scott Alexander JOHANNESMEYER, Robert Paul LUCKIN, Stephen Arlon MEISNER
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Publication number: 20210098565Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Inventors: Poornika FERNANDES, David Matthew CURRAN, Stephen Arlon MEISNER, Bhaskar SRINIVASAN, Guruvayurappan S. MATHUR, Scott William JESSEN, Shih Chang CHANG, Russell Duane FIELDS, Thomas Terrance LYNCH
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Patent number: 10608075Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.Type: GrantFiled: January 4, 2019Date of Patent: March 31, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bhaskar Srinivasan, Guru Mathur, Stephen Arlon Meisner, Shih Chang Chang, Corinne Ann Gagnet
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Publication number: 20190157379Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.Type: ApplicationFiled: January 4, 2019Publication date: May 23, 2019Inventors: Bhaskar Srinivasan, Guru Mathur, Stephen Arlon Meisner, Shih Chang Chang, Corinne Ann Gagnet
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Patent number: 10177215Abstract: A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the capacitor dielectric layer. The silicon oxy-nitride layer has an average index of refraction of 1.85 to 1.95 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. The upper plate is formed, leaving the lower silicon dioxide layer, the silicon oxy-nitride layer, and at least a portion of the upper silicon dioxide layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.Type: GrantFiled: October 25, 2017Date of Patent: January 8, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bhaskar Srinivasan, Guru Mathur, Stephen Arlon Meisner, Shih Chang Chang, Corinne Ann Gagnet
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Patent number: 8466569Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.Type: GrantFiled: March 26, 2009Date of Patent: June 18, 2013Assignee: Texas Instruments IncorporatedInventors: Stephen Arlon Meisner, Scott R. Summerfelt
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Patent number: 8431463Abstract: A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process.Type: GrantFiled: August 10, 2009Date of Patent: April 30, 2013Assignee: Texas Instruments IncorporatedInventors: Maxwell Walthour Lippitt, III, Stephen Arlon Meisner, Lee Alan Stringer, Stephen Fredrick Clark, Fred Percy Debnam, II, Byron Lovell Williams
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Patent number: 8236703Abstract: Methods for removing contaminants from a semiconductor device that includes a plurality of aluminum-comprising bond pads on a semiconductor surface of a substrate. A plurality of aluminum-including bond pads are formed on the semiconductor surface of the substrate. A patterned passivation layer is then formed on the semiconductor surface, wherein the patterned passivation layer provides an exposed area for the plurality of bond pads. Wet etching with a basic etch solution is used to etch a surface of the exposed area of the aluminum-including bond pads, wherein the wet etching removes at least 100 Angstroms from the surface of the bond pads to form a cleaned surface.Type: GrantFiled: September 11, 2008Date of Patent: August 7, 2012Assignee: Texas Instruments IncorporatedInventors: Alfred J. Griffin, Jr., Lisa A. Fritz, Lin Li, Lee Alan Stringer, Neel A. Bhatt, John Paul Campbell, Stephen Arlon Meisner, Charles Leighton
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Publication number: 20110029119Abstract: A manufacturing process including a controller method to generate a tool setting which includes a tool offset and a device offset. The controller method uses a device parameter measurement to update the tool offset and device offset. A tool weight and a device weight is assigned so that only one of the tool offset and device offset is significantly changed during the update. The process may be applied to semiconductor device manufacturing and particularly to integrated circuit fabrication.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Madhu Sudan RAMAVAJJALA, Kristi BUSHMAN, Robert Ray SPANGLER, Stephen Arlon MEISNER, Ronald Charles ROTH
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Publication number: 20100032803Abstract: A method is disclosed for passivating and contacting a capacitor in an IC above a top level of interconnect metallization, without adding process steps. Passivation is accomplished by a dielectric layer, part of the IC protective overcoat, deposited directly on the capacitor, overlapping the electrode edges. Contact is made to the top electrode of the capacitor by etching small capacitor vias during a bond pad via etch process, followed by depositing and patterning bond pad metal in the capacitor vias to connect the top electrode to other circuit elements in the IC. The top electrode thickness is increased to accommodate the bond pad via etch process.Type: ApplicationFiled: August 10, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Maxwell Walthour Lippitt, III, Stephen Arlon Meisner, Lee Alan Stringer, Stephen Fredrick Clark, Fred Percy Debnam, II, Byron Lovell Williams
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Publication number: 20090243123Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.Type: ApplicationFiled: March 26, 2009Publication date: October 1, 2009Applicant: Texas Instruments IncorporatedInventors: Stephen Arlon Meisner, Scott R. Summerfelt
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Publication number: 20090068847Abstract: Methods for removing contaminants from a semiconductor device that includes a plurality of aluminum-comprising bond pads on a semiconductor surface of a substrate. A plurality of aluminum-including bond pads are formed on the semiconductor surface of the substrate. A patterned passivation layer is then formed on the semiconductor surface, wherein the patterned passivation layer provides an exposed area for the plurality of bond pads. Wet etching with a basic etch solution is used to etch a surface of the exposed area of the aluminum-including bond pads, wherein the wet etching removes at least 100 Angstroms from the surface of the bond pads to form a cleaned surface.Type: ApplicationFiled: September 11, 2008Publication date: March 12, 2009Inventors: Alfred J. Griffin, JR., Lisa A. Fritz, Lin Li, Lee Alan Stringer, Neel A. Bhatt, John Paul Campbell, Stephen Arlon Meisner, Charles Leighton
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Patent number: 6985229Abstract: A method for nondestructively characterizing alignment overlay between two layers of a semiconductor wafer. An incident beam of radiation is directed upon the wafer surface and the properties of the resulting diffracted beam are determined, in one embodiment as a function of wavelength or incident angle. The spectrally or angularly resolved characteristics of the diffracted beam are related to the alignment of the overlay features. A library of calculated diffraction spectra is established by modeling a full range of expected variations in overlay alignment. The spectra resulting from the inspection of an actual wafer having alignment targets in at least two layers is compared against the library to identify a best fit to characterize the actual alignment. The results of the comparison may be used as an input for upstream and/or downstream process control.Type: GrantFiled: May 30, 2002Date of Patent: January 10, 2006Assignee: Agere Systems, Inc.Inventors: Cynthia C. Lee, Stephen Arlon Meisner, Thomas Michael Wolf, Alberto Santoni, John Martin McIntosh
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Patent number: 6893806Abstract: A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.Type: GrantFiled: August 15, 2002Date of Patent: May 17, 2005Assignee: Agere Systems, Inc.Inventors: Cheryl Anne Bollinger, Seungmoo Choi, William T. Cochran, Stephen Arlon Meisner, Daniel Mark Wroge, Gerard Zaneski
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Publication number: 20030223066Abstract: A method for nondestructively characterizing alignment overlay between two layers of a semiconductor wafer. An incident beam of radiation is directed upon the wafer surface and the properties of the resulting diffracted beam are determined, in one embodiment as a function of wavelength or incident angle. The spectrally or angularly resolved characteristics of the diffracted beam are related to the alignment of the overlay features. A library of calculated diffraction spectra is established by modeling a full range of expected variations in overlay alignment. The spectra resulting from the inspection of an actual wafer having alignment targets in at least two layers is compared against the library to identify a best fit to characterize the actual alignment. The results of the comparison may be used as an input for upstream and/or downstream process control.Type: ApplicationFiled: May 30, 2002Publication date: December 4, 2003Inventors: Cynthia C. Lee, Stephen Arlon Meisner, Thomas Michael Wolf, Alberto Santoni, John Martin McIntosh
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Publication number: 20030039928Abstract: A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.Type: ApplicationFiled: August 15, 2002Publication date: February 27, 2003Inventors: Cheryl Anne Bollinger, Seungmoo Choi, William T. Cochran, Stephen Arlon Meisner, Daniel Mark Wroge, Gerard Zaneski