Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface, wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.

Abstract: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to..said substrate surface, wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.

Abstract: A method of forming an integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the method includes depositing a first insulator layer over an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are formed in the first insulator layer, and the first insulator layer is etched to form a trench therein between the first and second conductive lines. A first conductive layer is deposited over the first and second conductive lines the said trench. A second insulator layer is deposited over the first conductive layer, and a second conductive layer is deposited over the second insulator layer. Then, a third conductive line is formed and disposed in the trench, the third conductive line overlying the second conductive barrier layer.

Abstract: An epitaxial base bipolar transistor including an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on a portion of the single crystal layer; a raised extrinsic base on a surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein the insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in the single crystal layer, wherein the emitter diffusion has an emitter diffusion junction depth.

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract: A method of forming an integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the method includes depositing a first insulator layer over an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are formed in the first insulator layer, and the first insulator layer is etched to form a trench therein between the first and second conductive lines. A first conductive layer is deposited over the first and second conductive lines the said trench. A second insulator layer is deposited over the first conductive layer, and a second conductive layer is deposited over the second insulator layer. Then, a third conductive line is formed and disposed in the trench, the third conductive line overlying the second conductive barrier layer.

Abstract: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface. wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.

Abstract: A method for fabricating a poly-poly capacitor integrated with a BiCMOS process which includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor; and forming an upper SiGe plate electrode during growth of a SiGe base region of a heterojunction bipolar transistor.

Abstract: Reliable metal oxide semiconductor (MOS) devices which exhibit little or no oxide breakdown at the Rx edge during device biasing are provided. The improved reliability is obtained by forming a contact to the polysilicon top conductor over a substantially thicker portion of the dielectric region. A method of fabricating the improved CMOS devices is also disclosed herein.

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract: An integrated circuit interconnect level capacitor is disclosed. In an exemplary embodiment, the capacitor includes a first insulator layer overlying an interconnect level surface of a semiconductor substrate having active devices. First and second conductive lines are provided in the first insulator layer and are separated by a trench defined by the first insulator layer and by sidewalls of the first and second conductive lines. A first conductive barrier layer overlies and connects the first and second conductive lines, and a second insulator layer overlies the first conductive barrier layer. A second conductive barrier layer overlies the second insulator layer, and a third conductive line is disposed in the trench and overlies the second conductive barrier layer.

Abstract: Reliable metal oxide semiconductor (MOS) devices which exhibit little or no oxide breakdown at the Rx edge during device biasing are provided. The improved reliability is obtained by forming a contact to the polysilicon top conductor over a substantially thicker portion of the dielectric region. A method of fabricating the improved CMOS devices is also disclosed herein.