Patents by Inventor Stephen C. Purcell
Stephen C. Purcell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180236220Abstract: An intravascular catheter is positionable within a blood vessel for use in transvenous stimulation of targets external to the wall of the blood vessel. The catheter includes a catheter body, a support at the distal end of the catheter body, and a plurality of electrodes carried by the support. At least a portion of the support being inflatable within the blood vessel to bias at least a portion of the plurality of electrodes into contact with the blood vessel wall.Type: ApplicationFiled: April 19, 2018Publication date: August 23, 2018Applicant: NeuroTronik IP Holding (Jersey) LimitedInventors: Richard A. Glenn, Stephen C. Purcell
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Patent number: 9974946Abstract: An intravascular catheter is positionable within a blood vessel for use in transvenous stimulation of targets external to the wall of the blood vessel. The catheter includes a catheter body, a support at the distal end of the catheter body, and a plurality of electrodes carried by the support. At least a portion of the support being inflatable within the blood vessel to bias at least a portion of the plurality of electrodes into contact with the blood vessel wall.Type: GrantFiled: April 7, 2015Date of Patent: May 22, 2018Inventors: Richard A Glenn, Stephen C Purcell
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Publication number: 20160296747Abstract: An intravascular catheter is positionable within a blood vessel for use in transvenous stimulation of targets external to the wall of the blood vessel. The catheter includes a catheter body, a support at the distal end of the catheter body, and a plurality of electrodes carried by the support. At least a portion of the support being inflatable within the blood vessel to bias at least a portion of the plurality of electrodes into contact with the blood vessel wall.Type: ApplicationFiled: April 7, 2015Publication date: October 13, 2016Inventors: Richard A. Glenn, Stephen C. Purcell
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Patent number: 8824819Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.Type: GrantFiled: November 28, 2011Date of Patent: September 2, 2014Assignee: ATI Technologies ULCInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Stephen C. Hale
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Patent number: 8381223Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: GrantFiled: July 25, 2011Date of Patent: February 19, 2013Inventors: Korbin Van Dyke, Paul W Campbell, Don A. Van Dyke, Ali Alasti, Stephen C. Purcell
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Publication number: 20120070094Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.Type: ApplicationFiled: November 28, 2011Publication date: March 22, 2012Applicant: ATI TECHNOLOGIES ULCInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Steve C. Hale
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Patent number: 8121828Abstract: A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.Type: GrantFiled: December 2, 2004Date of Patent: February 21, 2012Assignee: ATI Technologies ULCInventors: John S. Yates, Jr., David L. Reese, Paul H. Hohensee, Stephen C. Purcell, Korbin S. Van Dyke
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Patent number: 8086055Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.Type: GrantFiled: April 22, 2009Date of Patent: December 27, 2011Assignee: ATI Technologies ULCInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Steve C. Hale
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Publication number: 20110283293Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: ApplicationFiled: July 25, 2011Publication date: November 17, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Korbin Van Dyke, Paul Campbell, Don Van Dyke, Ali Alasti, Stephen C. Purcell
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Patent number: 7987465Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: GrantFiled: January 15, 2010Date of Patent: July 26, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Korbin Van Dyke, Paul W Campbell, Don A. Van Dyke, Ali Alasti, Stephen C. Purcell
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Publication number: 20100208826Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit, which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.Type: ApplicationFiled: April 22, 2009Publication date: August 19, 2010Applicant: ATI International SRLInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Steve C. Hale
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Publication number: 20100122262Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: ApplicationFiled: January 15, 2010Publication date: May 13, 2010Applicant: Advanced Micro Devices, Inc.Inventors: Korbin Van Dyke, Paul Campbell, Don Van Dyke, Ali Alasti, Stephen C. Purcell
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Patent number: 7661107Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: GrantFiled: January 18, 2000Date of Patent: February 9, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Korbin Van Dyke, Paul Campbell, Don A. Van Dyke, Ali Alasti, Stephen C. Purcell
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Patent number: 7574065Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.Type: GrantFiled: June 10, 2004Date of Patent: August 11, 2009Assignee: ATI International SRLInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Steve C. Hale
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Patent number: 7552165Abstract: Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa. The third mantissa is normalized to produce a final mantissa. The third mantissa and the final mantissa are correctly rounded as a result of the act of adding, so that the final mantissa does not require processing by a follow on rounding stage.Type: GrantFiled: May 27, 2005Date of Patent: June 23, 2009Inventor: Stephen C. Purcell
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Patent number: 7457937Abstract: Embodiments of the present invention recite a method and system for accessing data. In one embodiment of the present invention, a plurality of instances of data are stored in a memory device which comprises a plurality of memory modules disposed as an array of parallel columns. In response to receiving an indication that said plurality of instances of data is being accessed as a row of data, a first address translation table is accessed which describes the same row address in each of said plurality of memory modules wherein an instance of data is stored. Then, in response to receiving an indication that said plurality of instances of data is being accessed as a column of data, a second address translation table is accessed which describes a successive row address in each successive memory module wherein an instance of data is stored.Type: GrantFiled: February 9, 2006Date of Patent: November 25, 2008Assignee: Nvidia CorporationInventors: Christopher T. Cheng, Stephen C. Purcell
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Patent number: 7254231Abstract: A structure and associated method to implement encryption/decryption under the Data Encryption Standard (DES). Several additional instructions are included in the instruction set of a general purpose microprocessor to operate in conjunction with hardware included in a data path of the general purpose microprocessor. The additional instructions perform a portion of the DES algorithm, in particular, a portion of a DES round. The state information used at each step of the encryption portion of the DES algorithm is provided in various general purpose registers of the general purpose microprocessor. In one embodiment, all sixteen subkeys are selected prior to the DES step in the general processor after a DES key is known. In another embodiment, each subkey is selected during the round it is used. In yet another embodiment, each subkey is selected during the round it is used, as part of an additional instruction executed by the general purpose microprocessor.Type: GrantFiled: October 14, 1999Date of Patent: August 7, 2007Assignee: ATI International SRLInventors: Don Van Dyke, Korbin Van Dyke, Stephen C. Purcell
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Patent number: 7013456Abstract: A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.Type: GrantFiled: June 16, 1999Date of Patent: March 14, 2006Assignee: ATI International SRLInventors: Korbin S. Van Dyke, Paul H. Hohensee, David L. Reese, John S. Yates, Jr., T. R. Ramesh, Shalesh Thusoo, Gurjeet Singh Saund, Stephen C. Purcell, Niteen Aravind Patkar
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Patent number: 6978462Abstract: A computer having an instruction pipeline and profile circuitry. The profile circuitry detects and records, without compiler assistance for execution profiling, profile information describing a sequence of events occurring in the instruction pipeline. The sequence includes every event occurring during a profiled execution interval that matches time-independent selection criteria of events to be profiled. The recording continues until a predetermined stop condition is reached. The profile circuitry detects the occurrence of a predetermined condition, after a non-profiled interval of execution, and then commences the profiled execution interval.Type: GrantFiled: June 11, 1999Date of Patent: December 20, 2005Assignee: ATI International SRLInventors: Michael C. Adler, John S. Yates, Jr., David L. Reese, Paul H. Hohensee, Stephen C. Purcell
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Patent number: 6938198Abstract: A method for computing Ethernet checksums for implementing ECC processing within high performance digital transmission networks. The method includes the step of receiving an input data word and receiving an input CRC. The input data word can be 64 bits. The input CRC can be 32 bits. The input data word and the input CRC are combined using an exclusive-or function to obtain a data-CRC combination. The data-CRC combination is then positioned with respect to a time line reference. The data-CRC combination is positioned by extending the data-CRC combination with a number of future bits and shifting the extended data-CRC combination with respect to the time line reference. An output CRC is then computed for the extended data-CRC combination. The output CRC can be computed without regard to a number of valid data bits of the input data word.Type: GrantFiled: October 5, 2001Date of Patent: August 30, 2005Assignee: Broadband Royalty CorporationInventor: Stephen C. Purcell