Patents by Inventor Stephen Chou

Stephen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10551319
    Abstract: A fluidic chip includes at least one nanochannel array, the nanochannel array including a surface having a nanofluidic area formed in the material of the surface; a microfluidic area on said surface; a gradient interface area having a gradual elevation of height linking the microfluidic area and the nanofluidic area; and a sample reservoir capable of receiving a fluid in fluid communication with the microfluidic area. In another embodiment, a fluidic chip includes at least one nanochannel array, the nanochannel array includes a surface having a nanofluidic area formed in the material of the surface; a microfluidic area on said surface; and a gradient interface area linking the microfluidic area and the nanofluidic area, where the gradient interface area comprises a plurality of gradient structures, and the lateral spacing distance between said gradient structures decreases towards said nanofluidic area; and a sample reservoir capable of receiving a fluid in fluid communication with the microfluidic area.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: February 4, 2020
    Assignee: Princeton University
    Inventors: Han Cao, Jonas O. Tegenfeldt, Stephen Chou, Robert H. Austin
  • Publication number: 20170328835
    Abstract: A fluidic chip includes at least one nanochannel array, the nanochannel array including a surface having a nanofluidic area formed in the material of the surface; a microfluidic area on said surface; a gradient interface area having a gradual elevation of height linking the microfluidic area and the nanofluidic area; and a sample reservoir capable of receiving a fluid in fluid communication with the microfluidic area. In another embodiment, a fluidic chip includes at least one nanochannel array, the nanochannel array includes a surface having a nanofluidic area formed in the material of the surface; a microfluidic area on said surface; and a gradient interface area linking the microfluidic area and the nanofluidic area, where the gradient interface area comprises a plurality of gradient structures, and the lateral spacing distance between said gradient structures decreases towards said nanofluidic area; and a sample reservoir capable of receiving a fluid in fluid communication with the microfluidic area.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventors: Han Cao, Jonas O. Tegenfeldt, Stephen Chou, Robert H. Austin
  • Patent number: 9733185
    Abstract: The present invention relates to a device for interfacing nanofluidic and microfluidic components suitable for use in performing high throughput macromolecular analysis. Diffraction gradient lithography (DGL) is used to form a gradient interface between a microfluidic area and a nanofluidic area. The gradient interface area reduces the local entropic barrier to nanochannels formed in the nanofluidic area. In one embodiment, the gradient interface area is formed of lateral spatial gradient structures for narrowing the cross section of a value from the micron to the nanometer length scale. In another embodiment, the gradient interface area is formed of a vertical sloped gradient structure. Additionally, the gradient structure can provide both a lateral and vertical gradient.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: August 15, 2017
    Assignee: Princeton University
    Inventors: Han Cao, Jonas O. Tegenfeldt, Stephen Chou, Robert H. Austin
  • Patent number: 9298771
    Abstract: Disclosed herein are system, method, and computer program product embodiments for performing resource estimation for query optimization. An embodiment operates by generating a subplan for which an optimization process may be invoked, predicting performance and resource consumption for optimizing the subplan by measuring similarity between a hypergraph of the subplan and one or more etalon queries having known performance and resource consumption properties, selecting an algorithm for optimizing the subplan from a plurality of optimization algorithms based on the performance and resource consumption properties, and generating an optimized access plan using the selected algorithm.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: March 29, 2016
    Assignee: IAS Solutions, Inc.
    Inventors: Anisoara Nica, Stephen Chou
  • Publication number: 20140214798
    Abstract: Disclosed herein are system, method, and computer program product embodiments for performing resource estimation for query optimization. An embodiment operates by generating a subplan for which an optimization process may be invoked, predicting performance and resource consumption for optimizing the subplan by measuring similarity between a hypergraph of the subplan and one or more etalon queries having known performance and resource consumption properties, selecting an algorithm for optimizing the subplan from a plurality of optimization algorithms based on the performance and resource consumption properties, and generating an optimized access plan using the selected algorithm.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Inventors: Anisoara NICA, Stephen Chou
  • Patent number: 8333934
    Abstract: The present invention relates to a device for interfacing nanofluidic and microfluidic components suitable for use in performing high throughput macromolecular analysis. Diffraction gradient lithography (DGL) is used to form a gradient interface between a microfluidic area and a nanofluidic area. The gradient interface area reduces the local entropic barrier to nanochannels formed in the nanofluidic area. In one embodiment, the gradient interface area is formed of lateral spatial gradient structures for narrowing the cross section of a value from the micron to the nanometer length scale. In another embodiment, the gradient interface area is formed of a vertical sloped gradient structure. Additionally, the gradient structure can provide both a lateral and vertical gradient.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: December 18, 2012
    Assignee: Princeton University
    Inventors: Han Cao, Jonas O. Tegenfeldt, Stephen Chou, Robert H. Austin
  • Patent number: 7818808
    Abstract: In one embodiment, a processor mode is provided for guest software. The processor mode enables the guest software to operate at a privilege level intended by the guest software. When the guest software attempts to perform an operation restricted by the processor mode, the processor mode is exited to transfer control over the operation to a virtual-machine monitor, which runs outside this processor mode.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: October 19, 2010
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Richard Uhlig
  • Patent number: 7717696
    Abstract: Apparatus for double-sided imprint lithography of an apertured substrate comprises a pair of correspondingly apertured molds, a support for an assembly of the substrate and molds, and an alignment mechanism with radially movable elements for aligning the apertures of the molds and the substrate. The movable elements can be at least partially disposed in a spindle and can be removed radially outward by a conically tapered drive rod. Opposing surfaces of the substrate can then be imprinted in registration at the same time, preferably by fluid pressure imprint lithography.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: May 18, 2010
    Assignee: Nanonex Corp.
    Inventors: Stephen Chou, Linshu Kong, Colby Steere, Mingtao (Gary) Li, Hua Tan, Lin Hu
  • Publication number: 20080106003
    Abstract: An improved method of imprint lithography involves using fluid-induced pressure from electric or magnetic fields to press a mold onto a substrate having a moldable surface. In essence, the method comprises the steps of providing a substrate having a moldable surface, providing a mold having a molding surface and pressing the molding surface and the moldable surface together by electric or magnetic fields to imprint the molding surface onto the moldable surface. The molding surface advantageously comprises a plurality of projecting features of nanoscale extent or separation, but the molding surface can also be a smooth planar surface, as for planarization. The improved method can be practiced without mechanical presses and without sealing the region between the mold and the substrate.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 8, 2008
    Inventor: Stephen Chou
  • Publication number: 20080012184
    Abstract: The addition of thin coatings (less than and approaching monomolecular coatings) of persistent release materials comprising preferred compounds of the formula: RELEASE-M(X)n?1 RELEASE-M(X)n?m?1 Qm, or RELEASE-M(OR)n'1, wherein RELEASE is a molecular chain of from 4 to 20 atoms in length, preferably from 6 to 16 atoms in length, which molecule has either polar or non-polar properties; M is a metal atom, semiconductor atom, or atom; X is halogen or cyano, especially Cl, F, or Br; Q is hydrogen or alkyl group; m is the number of Q groups; R is hydrogen, alkyl or phenyl, preferably hydrogen or alkyl of 1 to 4 carbon atoms; and n is the valence?1 of M; and n?m?1 is at least 1 provides good release properties. The coated substrates are particularly good for a lithographic method and apparatus for creating ultra-fine (sub-25 nm) patterns in a thin film coated on a substrate is provided, in which a mold having at least one protruding feature is pressed into a thin film carried on a substrate.
    Type: Application
    Filed: July 5, 2007
    Publication date: January 17, 2008
    Inventor: Stephen Chou
  • Patent number: 7313669
    Abstract: In one embodiment, a method for supporting address translation in a virtual-machine environment includes creating a guest translation data structure to be used by a guest operating system for address translation operations, creating an active translation data structure based on the guest translation data structure, and periodically modifying the content of the active translation data structure to conform to the content of the guest translations data structure. The content of the active translation data structure is used by a processor to cache address translations in a translation-lookaside buffer (TLB).
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg
  • Patent number: 7272831
    Abstract: A method and apparatus for constructing host processor soft devices independent of the host processor operating system are provided. In one embodiment, a driver of a soft device is implemented in a virtual machine monitor (VMM), and the soft device is made available for use by one or more virtual machines coupled to the VMM. In an alternative embodiment, a software component of a soft device is implemented in a first virtual machine that is coupled to a VMM, and the soft device is made available for use by a second virtual machine coupled to the VMM.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Erik Cota-Robles, Stephen Chou, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Gilbert Neiger, Richard Uhlig
  • Patent number: 7225441
    Abstract: In one embodiment, a method for providing power management via virtualization includes monitoring the utilization of a host platform device by one or more virtual machines and managing power consumption of the host platform device based on the results of monitoring.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Michael Kozuch, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Sebastian Schoenberg, Richard Uhlig
  • Patent number: 7217562
    Abstract: The present invention relates to a device for interfacing nanofluidic and microfluidic components suitable for use in performing high throughput macromolecular analysis. Diffraction gradient lithography (DGL) is used to form a gradient interface between a microfluidic area and a nanofluidic area. The gradient interface area reduces the local entropic barrier to nanochannels formed in the nanofluidic area. In one embodiment, the gradient interface area is formed of lateral spatial gradient structures for narrowing the cross section of a value from the micron to the nanometer length scale. In another embodiment, the gradient interface area is formed of a vertical sloped gradient structure. Additionally, the gradient structure can provide both a lateral and vertical gradient.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: May 15, 2007
    Assignee: Princeton University
    Inventors: Han Cao, Jonas O. Tegenfeldt, Stephen Chou, Robert H. Austin
  • Publication number: 20070082457
    Abstract: A processing method for use in the fabrication of fabrication of nanoscale electronic, optical, magnetic, biological, and fluidic devices and structures, for filling nanoscale holes and trenches, for planarizing a wafer surface, or for achieving both filling and planarizing of a wafer surface simultaneously. The method has the initial step of depositing a layer of a meltable material on a wafer surface. The material is then pressed using a transparent mold while shining a light pulse through the transparent mold to melt the deposited layer of meltable material. A flow of the molten layer material fills the holes and trenches, and conforms to surface features on the transparent mold. The transparent mold is subsequently removed.
    Type: Application
    Filed: September 19, 2006
    Publication date: April 12, 2007
    Inventors: Stephen Chou, Bo Cui, Christopher Keimel
  • Publication number: 20070026686
    Abstract: In accordance with the invention, the structure of a patterned nanoscale or near nanoscale device (“nanostructure”) is repaired and/or enhanced by liquifying the patterned device in the presence of appropriate guiding conditions for a period of time and then permitting the device to solidify. Advantageous guiding conditions include adjacent spaced apart or contacting surfaces to control surface structure and preserve vertically. Unconstrained boundaries to permit smoothing of edge roughness. In an advantageous embodiment, a flat planar surface is disposed overlying a patterned nanostructure surface and the surface is liquified by a high intensity light source to repair or enhance the nanoscale features.
    Type: Application
    Filed: May 29, 2006
    Publication date: February 1, 2007
    Inventors: Stephen Chou, Qiangfei Xia
  • Publication number: 20070020772
    Abstract: The present invention relates to a device for interfacing nanofluidic and microfluidic components suitable for use in performing high throughput macromolecular analysis. Diffraction gradient lithography (DGL) is used to form a gradient interface between a microfluidic area and a nanofluidic area. The gradient interface area reduces the local entropic barrier to nanochannels formed in the nanofluidic area. In one embodiment, the gradient interface area is formed of lateral spatial gradient structures for narrowing the cross section of a value from the micron to the nanometer length scale. In another embodiment, the gradient interface area is formed of a vertical sloped gradient structure. Additionally, the gradient structure can provide both a lateral and vertical gradient.
    Type: Application
    Filed: September 28, 2006
    Publication date: January 25, 2007
    Applicant: Princeton University
    Inventors: Han Cao, Jonas Tegenfeldt, Stephen Chou, Robert Austin
  • Publication number: 20060127522
    Abstract: An apparatus for performing imprint lithography especially useful in creating patterns with ultrafine features on a substrate. The apparatus comprises a substrate having moldable surface carried on a first block, a mold having a molding surface carried on a second block, positioners for moving the first and second blocks relative to each other, a sensor of the relative positions of the blocks and a controller for controlling the relative positions of the blocks.
    Type: Application
    Filed: January 27, 2003
    Publication date: June 15, 2006
    Inventor: Stephen Chou
  • Patent number: 7035963
    Abstract: In one embodiment, a method for resolving address space conflicts includes detecting that a guest operating system attempts to access a region occupied by a first portion of a virtual machine monitor and relocating the first portion of the virtual machine monitor within the first address space to allow the guest operating system to access the region previously occupied by the first portion of the virtual machine monitor.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg
  • Patent number: 7020738
    Abstract: One embodiment of the invention is method for resolving address space conflicts between a virtual machine monitor and a guest operating system. The method includes allocating an address space for the operating system and an address space for the monitor. The method also includes mapping a portion of the monitor into the address space allocated for the operating system and the address space allocated for the monitor, and locating another portion of the monitor in the address space allocated for the monitor. The method also includes detecting that the operating system attempts to access a region occupied by the portion of the monitor within the address space allocated for the operating system, and relocating that portion of the monitor within that address space to allow the operating system to access the region previously occupied by that portion of the monitor.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Stephen Chou, Erik Cota-Robles, Stalinselvaraj Jevasingh, Alain Kagi, Michael Kozuch, Richard Uhlig, Sebastian Schoenberg