Abstract: A method for detection and location of air leaks in a pressure vessel, such as a spacecraft, includes sensing structure-borne ultrasound waveforms associated with turbulence caused by a leak from a plurality of sensors and cross correlating the waveforms to determine existence and location of the leak. Different configurations of sensors and corresponding methods can be used. An apparatus for performing the methods is also provided.

Abstract: A mass storage device motherboard or secondary board includes a bridging circuit. The bridging circuit converts signals from the mass storage device into USB signals. The bridging circuit can be provided by a chip that converts ATA/ATAPI signals into USB signals.

Abstract: A mass storage device motherboard or secondary board includes a bridging circuit. The bridging circuit converts signals from the mass storage device into USB signals. The bridging circuit can be provided by a chip that converts ATA/ATAPI signals into USB signals.

Abstract: An integrated circuit multiport memory supports synchronous access through a serial port. In operation, a multiport memory of the present invention is coupled to a free running clock signal and a clock enable signal for internally synchronizing serial access. The external clock enable signal prevents incrementing the sequence of serial access when serial access is interrupted. In a synchronous memory of the present invention, the write data signal need not be held after the active edge of the serial clock, since serial data hold time is made independent of serial access memory write timing parameters. When serial data signals are conveyed on a bidirectional line of a asynchronous serial data port of the present invention, a direction control circuit of the present invention is responsive to transfer and write enable signals and independent of the conventional serial output enable signal.

Abstract: An integrated circuit multiport memory supports synchronous access through a serial port. In operation, a multiport memory of the present invention is coupled to a free running clock signal and a clock enable signal for internally synchronizing serial access. The external clock enable signal prevents incrementing the sequence of serial access when serial access is interrupted. In a synchronous memory of the present invention, the write data signal need not be held after the active edge of the serial clock, since serial data hold time is made independent of serial access memory write timing parameters. When serial data signals are conveyed on a bidirectional line of a asynchronous serial data port of the present invention, a direction control circuit of the present invention is responsive to transfer and write enable signals and independent of the conventional serial output enable signal.