Abstract: An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.

Abstract: Systems and methods for circuits with substantially equal propagation delay while providing different drive strengths are disclosed. These systems and methods may allow for a circuit with a drive strength that is some ratio of an arbitrary strength full drive strength circuit. Additionally, these circuits may have substantially the same input capacitance and feedback current as the baseline drive circuit. The input of such a circuit may be coupled to three nodes, one of which is an inverter coupled to the logic to be driven, the second of which is dummy logic, and the third of which is an inverter the output of which is left floating.

Abstract: A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.

Abstract: Chip logic, a frequency multiplication and/or division, a temperature sensing circuit, and a power management circuit, are integrated on a very large scale integrated (VLSI) circuit chip. The temperature sensing circuit directly measures the chip temperature, producing a temperature output signal. The power management circuit, which is connected to the temperature sensing circuit and to the chip logic, responds to the temperature output signal and to a functional state of the chip logic to generate a control signal to the PLL. The PLL responds to the control signal to either stop the clock signal or modify the operating frequency of the clock signal, depending upon the state of the control signal.

Abstract: A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one the first and second interconnected signal paths.

Abstract: Compensation circuit means for inclusion in an off-chip driver circuit is provided to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. The compensation circuit means, which is coupled across the output transistor circuit of the off-chip driver, may comprise one or more serially connected diodes. The diode (or diodes) may be formed by the base collector junction of a bipolar transistor.

Abstract: A driver circuit for a capacitively loaded line employs the charge storage capacitance of a diode for raising the base of a driver transistor above the circuit power supply voltage level so as to pull up the line to within a transistor base-emitter voltage drop of the power supply voltage level. The driver is easily fabricated in integrated circuit form, as no capacitors, either on or off chip, are required.The driver circuit includes a driver transistor, the collector of which is connected to the power supply and the emitter of which is connected to the line. A switching transistor has an input voltage applied between its base and emitter. A diode is connected between the switching and driver transistors, the anode being connected to the base of the driver transistor, and the cathode being connected to the collector of the switching transistor.

Abstract: An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a periodic reference signal to a periodic on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock).

Abstract: An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc.The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip.For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock).