Patents by Inventor Stephen Daley
Stephen Daley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971081Abstract: A structural damper (2) having an acoustic black hole (5), at least one sensor (7), a damper structure (4), an actuator (8) configured to apply an actuating force to the damper structure (4) and a controller (H) configured to control the actuator in dependence on a signal from the at least one sensor so as to provide structural damping of a primary structure (3).Type: GrantFiled: March 23, 2020Date of Patent: April 30, 2024Assignee: BAE SYSTEMS PLCInventors: Stephen Daley, Kristian Edward Hook, Jordan Cheer
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Publication number: 20240035536Abstract: According to the present invention there is provided an active vibration control system comprising: a driving mechanism and a control mechanism comprising an electromagnetic actuator, the driving mechanism being operable to apply a force on a base structure to which the active vibration control system is attachable such that vibrations of the base structure are actively controllable by the application of said force, wherein the driving mechanism and control mechanism are relatively moveable such that the active vibration control system has at least two modes of vibration, and wherein movement of the driving mechanism causes movement of at least a part of the control mechanism.Type: ApplicationFiled: December 6, 2021Publication date: February 1, 2024Applicant: BAE SYSTEMS plcInventors: Suleiman Mahmoud Sharkh, Stephen Daley, Mehdi Hendijanizadeh
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Publication number: 20240035535Abstract: According to the present invention there is provided an active vibration control system comprising: an electromagnetic actuator and a control element, the electromagnetic actuator being operable to apply a force on a base structure to which the active vibration control system is attachable such that vibrations of the base structure are actively controllable by the application of said force, wherein the electromagnetic actuator and control element are relatively moveable such that the active vibration control system has at least two modes of vibration, and wherein movement of the electromagnetic actuator causes movement of at least a part of the control element.Type: ApplicationFiled: December 6, 2021Publication date: February 1, 2024Applicant: BAE SYSTEMS plcInventors: Suleiman Mahmoud Sharkh, Stephen Daley, Mehdi Hendijanizadeh
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Publication number: 20240035537Abstract: According to the present invention there is provided an active vibration control system comprising: an electromagnetic actuator; a magnetic element; and a solenoid, the electromagnetic actuator being operable to apply a force on a base structure to which the active vibration control system is attachable such that vibrations of the base structure are actively controllable by the application of said force, wherein the electromagnetic actuator is operable to cause movement of the magnetic element through the solenoid and the solenoid is operable to apply a force on the magnetic element.Type: ApplicationFiled: December 6, 2021Publication date: February 1, 2024Applicant: BAE SYSTEMS plcInventors: Suleiman Mahmoud Sharkh, Stephen Daley, Mehdi Hendijanizadeh
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Patent number: 11764257Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: GrantFiled: January 10, 2022Date of Patent: September 19, 2023Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11538769Abstract: A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.Type: GrantFiled: December 14, 2018Date of Patent: December 27, 2022Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta
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Patent number: 11417759Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.Type: GrantFiled: June 6, 2019Date of Patent: August 16, 2022Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
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Publication number: 20220170526Abstract: A structural damper (2) having an acoustic black hole (5), at least one sensor (7), a damper structure (4), an actuator (8) configured to apply an actuating force to the damper structure (4) and a controller (H) configured to control the actuator in dependence on a signal from the at least one sensor so as to provide structural damping of a primary structure (3).Type: ApplicationFiled: March 23, 2020Publication date: June 2, 2022Applicant: BAE SYSTEMS plcInventors: Stephen Daley, Kristian Edward Hook, Jordan Cheer
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Publication number: 20220130953Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11271076Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.Type: GrantFiled: July 19, 2019Date of Patent: March 8, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11245003Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: GrantFiled: July 19, 2019Date of Patent: February 8, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11233157Abstract: A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.Type: GrantFiled: September 28, 2018Date of Patent: January 25, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
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Publication number: 20210288180Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 11069772Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.Type: GrantFiled: December 14, 2018Date of Patent: July 20, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 11056586Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.Type: GrantFiled: September 28, 2018Date of Patent: July 6, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almem Losee
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Patent number: 10957759Abstract: A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.Type: GrantFiled: December 28, 2018Date of Patent: March 23, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 10903330Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.Type: GrantFiled: November 27, 2013Date of Patent: January 26, 2021Assignee: General Electric CompanyInventors: Richard Joseph Saia, Stephen Daley Arthur, Zachary Matthew Stum, Roger Raymond Kovalec, Gregory Keith Dudoff
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Methods of fabricating high voltage semiconductor devices having improved electric field suppression
Patent number: 10892237Abstract: Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.Type: GrantFiled: December 14, 2018Date of Patent: January 12, 2021Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta -
Publication number: 20200203477Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: ApplicationFiled: July 19, 2019Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Publication number: 20200203476Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.Type: ApplicationFiled: July 19, 2019Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov