Patents by Inventor Stephen Daley Arthur
Stephen Daley Arthur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200105944Abstract: A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
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Publication number: 20190363183Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.Type: ApplicationFiled: June 6, 2019Publication date: November 28, 2019Inventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
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Patent number: 10367089Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.Type: GrantFiled: March 27, 2012Date of Patent: July 30, 2019Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Joseph Darryl Michael, Tammy Lynn Johnson, David Alan Lilienfeld, Kevin Sean Matocha, Jody Alan Fronheiser, William Gregg Hawkins
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Patent number: 9735263Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.Type: GrantFiled: November 18, 2013Date of Patent: August 15, 2017Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Kevin Sean Matocha, Ramakrishna Rao, Peter Almern Losee, Alexander Viktorovich Bolotnikov
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Patent number: 9576868Abstract: A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.Type: GrantFiled: July 30, 2012Date of Patent: February 21, 2017Assignee: General Electric CompanyInventors: Joseph Darryl Michael, Stephen Daley Arthur
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Publication number: 20160307997Abstract: A semiconductor device may include a substrate comprising silicon carbide; a drift layer disposed over the substrate doped with a first dopant type; an anode region disposed adjacent to the drift layer, wherein the anode region is doped with a second dopant type; and a junction termination extension disposed adjacent to the anode region and extending around the anode region, wherein the junction termination extension has a width and comprises a plurality of discrete regions separated in a first direction and in a second direction and doped with varying concentrations with the second dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from an edge of the primary blocking junction.Type: ApplicationFiled: June 28, 2016Publication date: October 20, 2016Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Motocha, Richard Joseph Saia, Zachary Matthew Stum, Ljuibisa Dragolijub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
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Patent number: 9406762Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.Type: GrantFiled: May 15, 2013Date of Patent: August 2, 2016Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Matocha, Richard Joseph Saia, Zachary Matthew Stum, Ljubisa Dragoljub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
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Patent number: 9379189Abstract: A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.Type: GrantFiled: March 11, 2015Date of Patent: June 28, 2016Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Michah Sandvik, Stephen Daley Arthur
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Publication number: 20160087091Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.Type: ApplicationFiled: November 18, 2013Publication date: March 24, 2016Inventors: Stephen Daley Arthur, Kevin Sean MATOCHA, Ramakrishna RAO, Peter Almern LOSEE, Alexander Viktorovich BOLOTNIKOV
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Patent number: 9257283Abstract: A semiconductor device is disclosed along with methods for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide.Type: GrantFiled: August 6, 2012Date of Patent: February 9, 2016Assignee: General Electric CompanyInventors: Joseph Darryl Michael, Stephen Daley Arthur, Tammy Lynn Johnson, David Alan Lilienfeld
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Patent number: 9123798Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.Type: GrantFiled: December 12, 2012Date of Patent: September 1, 2015Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Kevin Sean Matocha, Ramakrishna Rao, Peter Losee, Alexander Viktorovich Bolotnikov
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Publication number: 20150236151Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.Type: ApplicationFiled: February 18, 2014Publication date: August 20, 2015Applicant: GENERAL ELECTRIC COMPANYInventors: James Jay McMahon, Ljubisa Dragoljub Stevanovic, Stephen Daley Arthur, Thomas Bert Gorczyca, Richard Alfred Beaupre, Zachary Matthew Stum, Alexander Viktorovich Bolotnikov
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Publication number: 20150187884Abstract: A transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Inventors: Avinash SRIKRISHNAN KASHYAP, Peter Michah SANDVIK, Stephen Daley ARTHUR
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Publication number: 20150144960Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: General Electric CompanyInventors: Richard Joseph Saia, Stephen Daley Arthur, Zachary Matthew Stum, Roger Raymond Kovalec, Gregory Keith Dudoff
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Publication number: 20150115284Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.Type: ApplicationFiled: May 15, 2013Publication date: April 30, 2015Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Matocha, Richard Joseph Saia, Zachary Matthew Stum, Ljubisa Dragoljub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
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Patent number: 9006027Abstract: An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.Type: GrantFiled: September 11, 2012Date of Patent: April 14, 2015Assignee: General Electric CompanyInventors: Zachary Matthew Stum, Ahmed Elasser, Stephen Daley Arthur, Stanislav I. Soloviev, Peter Almern Losee
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Patent number: 8987858Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.Type: GrantFiled: March 18, 2013Date of Patent: March 24, 2015Assignee: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Stephen Daley Arthur
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Publication number: 20140361315Abstract: A semiconductor device according to one embodiment having a first region comprising a first dopant type, a second region adjacent the first region haivng a second dopant type and a channel region. There is a third region segregated from the channel region having a second dopant type, wherein the third region substantially coincides with the second region.Type: ApplicationFiled: August 25, 2014Publication date: December 11, 2014Inventors: Zachary Matthew Stum, Stephen Daley Arthur, Kevin Sean Matocha, Peter Almern Losee
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Publication number: 20140264775Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: General Electric CompanyInventors: Avinash Srikrishnan Kashyap, Peter Micah Sandvik, Stephen Daley Arthur
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Patent number: 8815721Abstract: A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.Type: GrantFiled: December 17, 2010Date of Patent: August 26, 2014Assignee: General Electric CompanyInventors: Zachary Matthew Stum, Stephen Daley Arthur, Kevin Sean Matocha, Peter Almern Losee