Abstract: An illustrative computing device may include a processor and a non-transitory memory device for storing a data structure capable of being compressed, where the data structure includes a plurality of data elements and each of the plurality of data elements includes a date field and a quantity field. The computing device may process instructions to arrange the plurality of data elements in a consecutive series in date order based on a value stored in the date field of each data element, determine whether a gap appears in the consecutive series of data elements based on a value stored in the quantity field of each element, remove the determined gaps in each of the data elements, and repeat the determining and removing steps until a predetermined criterion has been reached.

Abstract: According to various aspects, disclosed are exemplary embodiments of systems and methods for providing performance training and development.

Abstract: A lure box comprising a box bottom and box top. The box bottom and box top can substantially enclose an interior space, but leave an access opening through which at least a portion of the interior space can be accessed. A lure shelf having a plurality of notches for hooking fishing lures and/or hooks can be proximate to the access opening. The lure box can also have a plurality of posts that fishing line can be wrapped around and/or between, such that a fishing lure or hook and a connected fishing line can be pulled from the lure box through the access opening when desired.

Abstract: The invention is in the field of using a computer to provide automated investment allocation advice, selection of investment securities, customization of the automated advice, execution of investment securities, maintenance/monitoring of investment portfolios and rebalancing of investment portfolios. A user is connected to the Internet. The user connects to the portfolio management program (PMP) host computer through the Internet. The user completes a questionnaire that the PMP uses to generate a suitable investment allocation and specific portfolio strategy recommendation. The user reviews the strategy and specific information about the strategy. The information is transmitted across the Internet to the user. The information transmitted includes historic and/or hypothetical performance, historical and/or hypothetical holdings, current securities selections of the strategy, and a description of the strategy's selection methodology.

Abstract: An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar spiral. A region of the substrate below the inductor are removed to lower the inductive Q factor.

Abstract: The present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, comprises a first capacitor electrode, such as copper, comprised of a portion of the damascene interconnect structure, an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.

Abstract: An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar spiral. A region of the substrate below the inductor are removed to lower the inductive Q factor.

Abstract: The present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, comprises a first capacitor electrode, such as copper, comprised of a portion of the damascene interconnect structure, an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.

Abstract: The present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, comprises a first capacitor electrode, such as copper, comprised of a portion of the damascene interconnect structure, an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.