Abstract: Architectures for a ferroelectric memory which avoids the half select phenomenon and the problems associated with destructive readout. Non-destructive readout is provided by measuring current through the ferroelectric memory as a measure of its resistance. Information is stored in the ferroelectric memory element by altering its resistance through a polarizing voltage. The half select phenomenon is avoided by using isolation techniques. In various embodiments, zener diodes or bipolar junction transistors are used for isolation.

Abstract: A method for dry anisotropic etching of semiconductor material by a reactive gas infused in the presence of a low-pressure plasma discharge uses a photoresist mask superposed on a semiconductive film with the slope of the photoresist edges defined within a critical angular range to allow selective formation of a protective polymer film which prevents lateral etching of the edges of the photoresist and sidewalls of the film, while not inhibiting vertical etching, thereby allowing precision definition of the etched pattern. A novel technique to determine the conditions of the photoresist sidewall geometry necessary for polymer film formation and predictable etching behavior encapsulates the film in a thick layer of photoresist, which after cleaving the structure permits selectively etching the photoresist to expose and retain the polymer film without deformation.

Abstract: A process is described which combine polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means.This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide "bump" at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

Abstract: A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means.This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide "bump" at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

Abstract: A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means.This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n-epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide "bump" at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

Abstract: A source of electrons or charged particles is contained in a baffled enclosure at less than atmospheric pressure. The source projects the electrons or charged particles to strike a target with a velocity which generates soft x-rays. The target is in a chamber at substantially atmospheric pressure in a gaseous environment which is only slightly dispersive and absorptive of the soft x-rays. Access to this chamber is provided to insert a mask and substrate for lithographing by the soft x-rays.

Abstract: An electrical voltage is connected between a flexible soft-X-ray mask and a substrate causing the mask to make intimate contact and thereby conform to slight irregularities of the surface of the X-ray sensitive polymer on the substrate to minimize the effect of these irregularities during exposure to soft-X-rays.