Patents by Inventor Stephen How
Stephen How has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110151391Abstract: The invention relates to a bracket for fixing to the exterior face of a tooth, the bracket having a base, which lies against the tooth and in which a trapezoid shape slot is configured to receive a wire bow. The base of the slot runs essentially perpendicularly in the oral cavity with elevated surface, thus retaining the wire bow, which exerts forces and torques in an essentially horizontal direction, in an optimum position in the slot. The unique form of the inventive brackets has a dimple concave female surface and a channel for attachments to passes through which would allow the female to receive a convex male surface extension from the attachments and form a locking mechanism between concave female surface and the attachment convex male extension when attachment is used during the Orthodontic treatment. This unique model of locking mechanism has created a new inventive platform in Orthodontics for interchangeable attachments.Type: ApplicationFiled: January 2, 2011Publication date: June 23, 2011Inventors: Jeng-Kang Richard Shih, William How-Hong Shih, Stephen How-Ping Shih
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Patent number: 7362702Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: GrantFiled: October 29, 2002Date of Patent: April 22, 2008Assignee: QLOGIC, CorporationInventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20080008202Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a viral entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: September 24, 2007Publication date: January 10, 2008Inventors: William Terrell, Tracy Edmonds, Wayland Jeong, Eric Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Patent number: 7292567Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: GrantFiled: October 31, 2002Date of Patent: November 6, 2007Assignee: QLogic CorporationInventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20070183421Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: March 30, 2007Publication date: August 9, 2007Inventors: William Terrell, Tracy Edmonds, Wayland Jeong, Eric Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Patent number: 7200144Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: GrantFiled: October 18, 2001Date of Patent: April 3, 2007Assignee: Qlogic, Corp.Inventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20030210686Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame"s destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: October 18, 2001Publication date: November 13, 2003Applicant: Troika Networds, Inc.Inventors: William Terrell , Wayland Jeong , Haun Muliadi , Norman Chan , Rexford Hill , Michael Nishimura , Stephen How , Eric Peterson , Tracy Edmond
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Publication number: 20030189936Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: October 31, 2002Publication date: October 9, 2003Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20030189930Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: October 29, 2002Publication date: October 9, 2003Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20030191857Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: October 30, 2002Publication date: October 9, 2003Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Patent number: 5920572Abstract: A transport stream decoder/demultiplexer is provided which includes a program clock recovery circuit for recovering a program clock from program clock reference (PCR) values contained in selected transport packets. A processor is provided for extracting elementary stream data from transport packets labeled with packet identification codes (PIDs) that are specified by a host processor. The processor separately stores the elementary stream data of each stream. A host processor interface is also provided for transferring data between an external host processor and the program clock recovery circuit. A memory manager may be provided for storing the data extracted by the processor for each elementary stream in a corresponding queue. The queues may be maintained by the memory manager in an external RAM. A descrambler interface may be provided for transferring scrambled data and data derived from conditional access information between the processor and an external descrambler.Type: GrantFiled: January 11, 1996Date of Patent: July 6, 1999Assignee: Divicom Inc.Inventors: Emanuel Washington, Mike Perkins, Brian Johnson, Stephen How, Nolan Daines, Tom Ayers, Keith Vertrees