Abstract: A digital input/output interface for use with two digital circuits connected by a transmission line having a characteristic impedance Z.sub.0 includes a current driver in one of the digital circuits and a current receiver in the other digital circuit. The current driver is configured to generate a current in the transmission line when a digital signal is applied to the current driver. The current receiver includes a current conversion element connected to the transmission line at an input node through an input impedance Z.sub.in and adapted to convert the current in the transmission line into an output voltage, and an active termination element configured to actively adjust the input impedance Z.sub.in to match the characteristic impedance Z.sub.0 of the transmission line. An impedance transforming receiver for use with a transmission line having a small characteristic impedance Z.sub.

Abstract: A detector for electromagnetic radiation includes a high Q, low loss antenna and a low noise amplifier requiring a high input impedance. In the preferred embodiment, the antenna comprises a low resistance, superconductive coil. The antenna forms a resonant circuit with a low loss capacitor, optionally a capacitor including superconductors. The output of the resonant circuit is provided as input to the semiconductor amplifier. In the preferred embodiment, junction FETs, preferably arranged in a cascode pair, are included in the semiconductor amplifier. In one aspect of the invention, feedback is provided from the output of the amplifier to its input. Effective loading of the antenna results, lowering the Q of the antenna, and broadening the bandwidth of the detector. Optimum matching of the antenna to the noise factor of the amplifier is achieved.

Abstract: A dynamic logic circuit (AND or OR) utilizes one depletion-mode metal-semiconductor FET for precharging an internal node A, and a plurality of the same type of FETs in series, or a FET in parallel with one or more of the series connected FETs for implementing the logic function. A pair of FETs are connected to provide an output inverter with two series diodes for level shift. A coupling capacitor may be employed with a further FET to provide level shifting required between the inverter and the logic circuit output terminal. These circuits may be cascaded to form a domino chain.