Abstract: A multiplexed address/data signal bus capable of supporting multiple bus masters includes a group of control signal lines "shared" by each bus requestor device (BRD) coupled to the bus and a group of control signal lines "replicated" into sets, one for each BRD. The bus arrangement includes a central arbitration unit located in a host bus interface (HBI) which controls BRD access to the bus. A selection control signal is provided to select a set of replicated control signals corresponding to a current bus master. Bus isolation units (BIUs) are provided to isolate the BRDs from the shared control signals, thereby allowing multiple BRDs to "simultaneously" utilize the signal bus in order to execute multiple bus transactions in parallel.