Abstract: A mass storage cabinet having passive device position sensing and including shelves for racking device enclosures. A cabinet bus is linked to the shelves and adapted to provide a unique shelf identifier signal to each of the shelves. The cabinet includes a device providing a cabinet identifier to the shelves. The cabinet bus includes junction boxes having first and second sets of sensing wires and a side connectors linked to the shelves for providing the shelf identifier signal from the first and second sets of sensing wires. To provide a different signal at each junction box, the sensing wires in the first set are moved one position and the sensing wires in the second set are moved one position prior to the connection to an adjacent junction box. An additional sensing wire is linked to the side connectors and grounded and ungrounded at each side connector to alter the signal.

Abstract: A controller for positioning on a shelf of a cabinet within a mass storage system for controlling communication among device enclosures in a reporting group. The controller includes an interface to a data communication loop linking device enclosures each including disk drives positioned on one or more cabinets. The interface is used to transmit control commands. A cabinet bus interface controller is provided and linked to a cabinet bus in the cabinet to receive enclosure reporting messages from the device enclosures to collect environment information. The cabinet bus interface transmits reporting messages onto the cabinet bus to provide environmental information. The interface controller determines the shelf location of the controller within the cabinet from signals on the cabinet bus and receives the cabinet identifier over the cabinet bus. A processor is linked to the interface controller and functions to create and issue the control commands to the loop interface.

Abstract: A system and method for identifying a failed storage device in a storage system comprising a plurality of storage devices connected by a ring-type network is disclosed. In one embodiment, when a storage device fails, all storage devices on the ring-type network are disconnected to re-establish communication on the ring-type network. An iterative process of connecting a subset of storage devices to the ring-type network and testing communication on the ring-type network is performed until communication on the ring-type network is re-established. Then, individual storage devices are connected to the ring-type communication until the connection of a storage device causes communication on the ring-type network to fail, thereby identifying the failed storage device. In another embodiment, devices in a reporting group are tested on a shelf-by-shelf basis.

Abstract: A storage system capable of selectively presenting logical units to one or more host computing systems. The storage system comprises one or more persistent storage devices arranged as logical units; an array controller controlling and coordinating the operations of the persistent storage devices; a memory accessible by the array controller; and a configuration table stored in the memory, the configuration table containing one or more entries governing the interactions between the logical units and the one or more host computing systems.

Abstract: An apparatus and method for synchronizing a cache mode in a cache memory system in a computer to protect cache operations. The cache memory system has a first controller and a second controller and two cache modules and operates in a plurality of cache modes. The cache mode is stored as metadata in the cache modules and is detected by the first controller to determine the cache mode. Lock signals in the first controller are set in accordance with the cache mode detected to set the cache mode state in the first controller. The second controller copies the cache mode state from the first controller to synchronize both controllers in the same cache mode state. After a failure of the second controller, the first controller may lock access to both caches to recover data previously accessed by the second controller. The second controller restarts and copies the cache mode state from the first controller, so that both controllers return to the cache mode state prior to the failure of the second controller.

Abstract: Metadata described herein on a RAID array includes both device metadata and RAIDset metadata. The device metadata has a device FE bit on each storage device corresponding to each RAID protected block on the storage device. The device FE bit indicates if a corresponding RAID protected block is consistent and thereby useable to regenerate data in another RAID protected block in the corresponding RAID protected block's sliver. The user data also has a forced error bit to indicate if a physical block in the user block has inconsistent data, the RAIDset FE bit. The RAID array of storage devices has user data blocks on each storage device RAID protected by being distributed as slivers of blocks across the RAID array of storage devices. Each sliver has a plurality of user data blocks and one parity block. The RAIDset metadata has the RAIDset FE bit corresponding to each RAID protected user data block in the RAID array.

Abstract: A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.

Abstract: In a SCSI subsystem having mixed wide and narrow SCSI devices installed, a method and apparatus is provided for detecting a narrow SCSI device illegally installed at a slot assigned to a wide SCSI device. To detect the narrow SCSI device installed at an illegal location, high ID and low ID SCSI bus address pairs are set as test pairs for the SCSI subsystem. The low ID is the alias of the high ID if a narrow SCSI device is installed at the high ID slot. To detect a conflict with a controller ID, a non-responsive ID bus address corresponding to a slot known to be unused is called. A response to this call indicates a narrow SCSI device is installed at the high ID of the test pair and the narrow SCSI device at the high ID has configured to an alias bus address matching the controller ID. To detect a present conflict between SCSI devices, the low ID bus address in the test pair is called.

Abstract: A RAID array includes redundant storage devices. Data is distributed across the storage devices, and organized as slivers of RAID protected data blocks. This redundancy provides for the reconstruction of valid data when data at a particular data block of a sliver is found to be inconsistent. However, when more than one data block of a sliver is found to have inconsistent data, reconstruction of the inconsistent data blocks may not be possible. Nonetheless, data consistency can still be restored to that sliver. Consistency is restored to such a sliver by replacing any inconsistent data in a data block with predetermined data and reconstructing the parity data block using the predetermined data. Other data in the RAID array keeps track of those data blocks with the predetermined data to indicate that such blocks do not contain valid data.

Abstract: A data block in a RAID array is reconstructed under the control of metadata recorded on the RAID array. The RAID array has a plurality of members, each member being a data storage device. The metadata includes device metadata for data blocks recorded on each member and RAIDset metadata for RAID protected data blocks recorded across the members of the RAID array. The RAID protected data blocks include user data blocks, RAIDset metadata blocks and parity data blocks. The data blocks are reconstructed by detecting from a device FE bit in the device metadata that a bad data block corresponding to or associated with the device FE bit needs to be reconstructed. The data is read from each data block, other than the bad data block, in the same RAID sliver with bad data block. A RAID sliver of data blocks includes all the data blocks in a RAID protected sliver of data blocks.

Abstract: Provided herein is a method and apparatus for host transparent storage controller failover and failback. A controller is capable of assuming the identity of a failed controller while continuing to respond to its own SCSI ID or IDs in such a way that all SCSI IDs and associated units (LUNS) of the failed controller are effectively taken over by the surviving controller. This "failover" behavior is transparent to any attached host computers and is treated by such attached hosts as a powerfail condition. The symmetric operation of returning the targets (IDs) and units (LUNs) to the previously failing controller ("failback") is likewise transparent.

Abstract: An improved method for testing a large memory array of a digital computer system during system initialization or reset. First, the memory test method checks the whole memory array for addressing faults, and then a first portion of the memory array for both address line and data failures. While operational firmware is loaded into and begins to execute from the tested first portion, the remaining address locations of the array are tested in a background task. Beginning at the last address of the first portion, sequential portions of memory array are tested and released to the functional code as they have been tested.

Abstract: A method of testing a memory containing data being used by a processor uses a dedicated diagnostic test page (DTP) and diagnostic status page (DSP) in the memory under test to carry out the testing. The DTP is address-tested and pattern-tested first. Then, each page of the memory is in turn copied to the DTP, tested, and then restored from the DTP. During the test, the address of the page being tested is stored in the DSP along with a valid flag and an error detection code (EDC). A recovery procedure uses the information on the DSP to restore memory pages if the test is interrupted.