Abstract: Power protection loops for amplifier chain elements are disclosed. In one aspect, an amplifier chain may have a power detection circuit detect power within the amplifier chain. When the power exceeds a threshold, a control circuit limits amplification provided by amplifier element(s) within the amplifier chain to throttle or lower power levels within the amplifier chain, thereby protecting elements within the amplifier chain. In this fashion, not only may the amplifier element(s) be protected, but also acoustic filter elements may be protected. The threshold used to throttle or lower the power levels may be based on one or more of: a supply voltage, a sensed temperature, and a mode (e.g., 2G, 3G, 4G, 5G). By protecting these elements, these elements survive power surges instead of failing.

Abstract: A protection circuit for an acoustic filter and/or a power amplifier is disclosed. In one aspect, the protection circuit includes a bidirectional coupler that helps secure a measurement of power at an antenna. The power measurement is compared to a threshold by a detector, and if the power measurement is above the threshold, a signal is sent that causes debiasing of a power amplifier stage, which reduces power levels of signals being amplified by the power amplifier stage and correspondingly lowers the power level going through a filter associated with the power amplifier stage. By lowering the power level going through the power amplifier stage and the filter, both elements are protected against over power conditions allowing functionality to be maintained.

Abstract: A power amplifier using multi-path common-mode feedback loops for radio frequency linearization is disclosed. In one aspect, a complementary metal oxide semiconductor (CMOS) power amplifier containing cascoded n-type field effect transistors (NFETs) and cascoded p-type FETs (PFETs) may have a common-mode feedback network and provides bias voltages that are dynamically varying with the signal power to keep the output common-mode fixed around a half-supply level, while the small-signal and large-signal transconductances of the FET's are kept balanced. A further feedback network may be associated with the supply voltage to assist in providing a symmetrical supply signal. The symmetrical supply signal allows for supply variations without introducing distortion for the power amplifier stage.

Abstract: A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator, but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop or the over-voltage protection loop contribute to an over-current protection signal.

Abstract: A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.

Abstract: Reduced flyback electrostatic discharge (ESD) surge protection is disclosed. An ESD protection circuit differentiates ESD events from normal power on based on supply rise time. During an ESD protection cycle, the ESD protection circuit briefly clamps a supply on an identified ESD edge to limit and protect an electronic device from high voltage and/or current. In some cases, a surge condition may occur as the ESD protection circuit becomes disabled, such as in the presence of a fast rise time power supply. When the power supply is also inductive, a flyback voltage overshoot at the sudden release of the ESD clamp can result in permanent over voltage-related device damage. An exemplary ESD protection circuit includes a controlled disable state which reduces or eliminates flyback during such a surge by gradually ramping down current from the ESD protection cycle.

Abstract: Reduced flyback electrostatic discharge (ESD) surge protection is disclosed. An ESD protection circuit differentiates ESD events from normal power on based on supply rise time. During an ESD protection cycle, the ESD protection circuit briefly clamps a supply on an identified ESD edge to limit and protect an electronic device from high voltage and/or current. In some cases, a surge condition may occur as the ESD protection circuit becomes disabled, such as in the presence of a fast rise time power supply. When the power supply is also inductive, a flyback voltage overshoot at the sudden release of the ESD clamp can result in permanent over voltage-related device damage. An exemplary ESD protection circuit includes a controlled disable state which reduces or eliminates flyback during such a surge by gradually ramping down current from the ESD protection cycle.

Abstract: A power amplifier system having a power amplifier with a signal input and a signal output, bias circuitry coupled to the signal input, and a radio frequency (RF) peak detector having an input coupled to the signal output is disclosed. The RF peak detector is configured to generate a peak voltage signal. Temperature-compensated overvoltage protection circuitry coupled between an output of the RF peak detector and a control input of the bias circuitry is configured to respond to the peak voltage signal crossing over a predetermined peak voltage threshold and to provide an overvoltage protection control signal to cause the bias circuitry to adjust biasing for the power amplifier to reduce an overvoltage condition at the RF peak detector input.

Abstract: A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.

Abstract: A power amplifier system having a power amplifier with a signal input and a signal output, bias circuitry coupled to the signal input, and a radio frequency (RF) peak detector having an input coupled to the signal output is disclosed. The RF peak detector is configured to generate a peak voltage signal. Temperature-compensated overvoltage protection circuitry coupled between an output of the RF peak detector and a control input of the bias circuitry is configured to respond to the peak voltage signal crossing over a predetermined peak voltage threshold and to provide an overvoltage protection control signal to cause the bias circuitry to adjust biasing for the power amplifier to reduce an overvoltage condition at the RF peak detector input.

Abstract: A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.

Abstract: A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.

Abstract: A radio frequency switch made up of a plurality of switch cells coupled in series between a first node and a second node is disclosed. Each of the plurality of switch cells has a switch field-effect transistor (FET) having a switch drain terminal, a switch source terminal, a switch gate terminal, and a switch body terminal. A body bias network having a first body bias FET with a first drain terminal coupled to the switch body terminal includes a first cross-FET with a second drain terminal coupled to a first source terminal of the first bias body FET and a second source terminal coupled to the switch gate terminal. A second body bias FET has a third drain terminal coupled to the switch body terminal, and a second cross-FET has a fourth drain terminal coupled to a third source terminal of the second body bias FET.

Abstract: The present disclosure relates to a power amplifier (PA) system provided in a semiconductor device and having feed forward gain control. The PA system comprises a transmit path and control circuitry. The transmit path is configured to amplify an input radio frequency (RF) signal and comprises a first tank circuit and a PA stage. The control circuitry is configured to detect a power level associated with the input RF signal and control a first bias signal provided to the PA stage based on a first function of the power level and control a quality factor (Q) of the first tank circuit based on a second function of the power level.

Abstract: A radio frequency switch made up of a plurality of switch cells coupled in series between a first node and a second node is disclosed. Each of the plurality of switch cells has a switch field-effect transistor (FET) having a switch drain terminal, a switch source terminal, a switch gate terminal, and a switch body terminal. A body bias network having a first body bias FET with a first drain terminal coupled to the switch body terminal includes a first cross-FET with a second drain terminal coupled to a first source terminal of the first bias body FET and a second source terminal coupled to the switch gate terminal. A second body bias FET has a third drain terminal coupled to the switch body terminal, and a second cross-FET has a fourth drain terminal coupled to a third source terminal of the second body bias FET.

Abstract: The present disclosure relates to a power amplifier (PA) system provided in a semiconductor device and having feed forward gain control. The PA system comprises a transmit path and control circuitry. The transmit path is configured to amplify an input radio frequency (RF) signal and comprises a first tank circuit and a PA stage. The control circuitry is configured to detect a power level associated with the input RF signal and control a first bias signal provided to the PA stage based on a first function of the power level and control a quality factor (Q) of the first tank circuit based on a second function of the power level.