Patents by Inventor Stephen Keckler

Stephen Keckler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110060889
    Abstract: Examples of a system, method and computer accessible medium are provided to generate a predicate prediction for a distributed multi-core architecture. Using such system, method and computer accessible medium, it is possible to intelligently encode approximate predicate path information on branch instructions. Using this statically generated information, distributed predicate predictors can generate dynamic predicate histories that can facilitate an accurate prediction of high-confidence predicates, while minimizing the communication between the cores.
    Type: Application
    Filed: September 9, 2009
    Publication date: March 10, 2011
    Applicant: Board of Regents, University of Texas System
    Inventors: Doug Burger, Stephen Keckler, Hadi Esmaeilzadeh
  • Publication number: 20050132140
    Abstract: An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).
    Type: Application
    Filed: October 8, 2004
    Publication date: June 16, 2005
    Inventors: Doug Burger, Stephen Keckler, Changkyu Kim
  • Publication number: 20050005084
    Abstract: A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive and store instructions, an instruction wakeup unit to match the input data to the instructions, at least one execution unit to execute the instructions, using the input data to produce output data, and at least one output port capable of being coupled to at least one second other computation node. The node may also include a router to direct the output data from the output port(s) to the second other node. A system according to various embodiments of the invention includes and external instruction sequencer to fetch a group of instructions, and one or more interconnected, preselected computational nodes.
    Type: Application
    Filed: April 22, 2004
    Publication date: January 6, 2005
    Inventors: Douglas Burger, Stephen Keckler, Karthikeyan Sankaralingam, Ramadass Nagarajan