Patents by Inventor Stephen Keetai Park
Stephen Keetai Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6881665Abstract: A method is provided, the method comprising forming a dielectric layer above a structure layer, forming a hard mask layer above the dielectric layer, and forming at least one trench opening and at least one upper portion of a first via opening in the dielectric layer through the hard mask layer. The method also comprises forming a low viscosity photoresist layer above the at least one trench opening and the at least one upper portion of the first via opening in the dielectric layer.Type: GrantFiled: August 9, 2000Date of Patent: April 19, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Ting Yiu Tsui, Stephen Keetai Park, Christian Zistl
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Patent number: 6756297Abstract: A method is provided for forming a copper interconnect, the method including forming a sacrificial dielectric layer above a structure layer, forming an opening in the sacrificial dielectric layer and forming a copper layer above the sacrificial dielectric layer and in the opening. The method also includes forming the copper interconnect by removing portions of the copper layer above the sacrificial dielectric layer, leaving the copper interconnect in the opening. The method further includes removing the sacrificial dielectric layer above the structure and adjacent the copper interconnect, and forming a low dielectric constant dielectric layer above the structure and adjacent the copper interconnect.Type: GrantFiled: October 29, 2001Date of Patent: June 29, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Stephen Keetai Park
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Patent number: 6682978Abstract: The present invention is directed to an integrated circuit having an increased gate coupling capacitance. The integrated circuit includes a substrate having a surface, the substrate having a trench extending below the surface. A trench fill material is disposed in the trench and has a portion extending above the surface. A first conductive layer is adjacent the trench fill material and has a portion extending over the portion of the insulative material. An insulative layer is adjacent the first conductive layer and a second conductive layer is adjacent the insulative layer. The present invention further is directed to a method of fabricating an integrated circuit on a substrate including the steps of forming a trench in the substrate, the trench extending below a surface of the substrate; providing a trench fill material in the trench such that the trench fill material extends above the surface of the substrate; and providing a first conductive layer over at least a portion of the trench fill material.Type: GrantFiled: February 15, 2000Date of Patent: January 27, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Stephen Keetai Park, Steven C. Avanzino
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Patent number: 6576949Abstract: The present invention is directed to an integrated circuit having an optimized gate coupling capacitance. The integrated circuit includes a substrate defining a trench therein. A first conductive layer has a portion which extends into the trench. The first conductive layer defines a channel fabricated by a blanket etching step. An insulative layer is adjacent the first conductive layer. A second conductive layer is adjacent the insulative layer. The present invention is further directed to a method of fabricating an integrated circuit. The method includes forming a trench in the substrate, filling the trench with a trench fill material, etching the trench fill material until an upper surface of the trench fill material is below an upper surface of the substrate, providing a first conductive layer over at least a portion of the trench fill material, and blanket etching the first conductive layer until the portion is exposed.Type: GrantFiled: August 30, 1999Date of Patent: June 10, 2003Assignee: Advanced Micro Devices, Inc.Inventor: Stephen Keetai Park
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Patent number: 6486506Abstract: An integrated circuit is designed to reduce charge gain and charge loss in a flash memory or flash programmable read-only memory. Charge gain and loss caused by moisture or hydrogen diffusion or alternately small contact-to-floating gate distance is reduced by a capping layer disposed over a gate stack and a base layer of the flash memory. The capping layer includes a buffer layer, a first insulative layer, and a second insulative layer. The etch characteristics of at least the first and second insulative layer differs from an interlevel dielectric to control the dimensions of a contact extending through the interlevel dielectric and the capping layer to the base layer.Type: GrantFiled: March 23, 2000Date of Patent: November 26, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Stephen Keetai Park, Jeffrey A. Shields
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Publication number: 20020155694Abstract: A method is provided for forming a copper interconnect, the method including forming a sacrificial dielectric layer above a structure layer, forming an opening in the sacrificial dielectric layer and forming a copper layer above the sacrificial dielectric layer and in the opening. The method also includes forming the copper interconnect by removing portions of the copper layer above the sacrificial dielectric layer, leaving the copper interconnect in the opening. The method further includes removing the sacrificial dielectric layer above the structure and adjacent the copper interconnect, and forming a low dielectric constant dielectric layer above the structure and adjacent the copper interconnect.Type: ApplicationFiled: October 29, 2001Publication date: October 24, 2002Applicant: Advanced Micro Devices, Inc.Inventor: Stephen Keetai Park
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Patent number: 6420104Abstract: A method of reducing contact size in an integrated circuit includes providing an insulating layer over a semiconductor substrate including a plurality of gate structures, creating an aperture extending through the insulating layer and having side walls, providing a spacer on the side walls of the aperture, and providing a contact in the aperture. The lateral sides of the contact abut the spacer. A contact structure is also disclosed in which a spacer separates a contact from a gate structure to avoid charge gain or loss between the contact and gate structure.Type: GrantFiled: November 3, 2000Date of Patent: July 16, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Bharath Rangarajan, Stephen Keetai Park, Guarionex Morales
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Patent number: 6410443Abstract: The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.Type: GrantFiled: February 22, 2000Date of Patent: June 25, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Steven C. Avanzino, Stephen Keetai Park, Kashmir S. Sahota, David H. Matsumoto, Mark Ramsbey
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Patent number: 6355555Abstract: A method is provided for forming a copper interconnect, the method including forming a sacrificial dielectric layer above a structure layer, forming an opening in the sacrificial dielectric layer and forming a copper layer above the sacrificial dielectric layer and in the opening. The method also includes forming the copper interconnect by removing portions of the copper layer above the sacrificial dielectric layer, leaving the copper interconnect in the opening. The method further includes removing the sacrificial dielectric layer above the structure and adjacent the copper interconnect, and forming a low dielectric constant dielectric layer above the structure and adjacent the copper interconnect.Type: GrantFiled: January 28, 2000Date of Patent: March 12, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Stephen Keetai Park
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Patent number: 6306758Abstract: A graded cap layer that reduces the overall height of a layer stack and provides for increased process control during subsequent patterning of the layer stack, is described with a method of making the same. The graded cap layer is configured to function as a cap layer to prevent an underlying silicide layer from lifting, a barrier layer to prevent the underlying silicide layer from being oxidized during subsequent processes, a stop layer to prevent over-etching during subsequent self-aligned source (SAS) patterning processes, and/or an anti-reflective coating (ARC) to improve the resolution of subsequent patterning processes. The graded cap layer is a relatively thin layer of silicon oxynitride with varying concentrations of nitrogen. The cap layer is deposited in a single chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) chamber.Type: GrantFiled: May 10, 2000Date of Patent: October 23, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Stephen Keetai Park
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Patent number: 6303486Abstract: A method is provided for forming a copper interconnect, the method including forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first copper structure in the first opening. The method also includes forming a sacrificial dielectric layer above the first dielectric layer and above the first copper structure, forming a second opening in the sacrificial dielectric layer above at least a portion of the first copper structure, and forming a second copper structure in the second opening, the second copper structure contacting the at least the portion of the first copper structure. The method further includes removing the sacrificial dielectric layer above the first dielectric layer and adjacent the second copper structure, and forming the copper interconnect by annealing the second copper structure and the first copper structure.Type: GrantFiled: January 28, 2000Date of Patent: October 16, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Stephen Keetai Park
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Patent number: 6287917Abstract: A process for fabricating an MNOS device includes the steps of forming a hardmask containing at least first and second openings over a core array area of a semiconductor substrate. An angle doping process is carried out to form halo regions in precise locations within the substrate at the edges of the first and second openings in the hardmask. Another doping process is carried out to form buried bit-lines in the substrate using the hardmask as a doping mask. Once the halo regions and the buried bit-lines are formed, the hardmask is removed and a composite dielectric layer is formed overlying the substrate.Type: GrantFiled: September 8, 1999Date of Patent: September 11, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Stephen Keetai Park, Tim Thurgate, Bharath Rangarajan
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Patent number: 6265294Abstract: A fabrication method reduces the amount of discoloration on interlevel dielectric layers due to anti-reflective coatings (ARC). The invention utilizes a barrier layer, such as, silicon nitride (SiN) that prevents the anti-reflective coating from contacting the interlevel dielectric layer (ILD0). The anti-reflective coating can be silicon oxynitride (SiON) deposited by LPCVD or PECVD.Type: GrantFiled: August 12, 1999Date of Patent: July 24, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Stephen Keetai Park, Guarionex Morales, Bharath Rangarajan, Jeff Shields
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Patent number: 6265273Abstract: A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.Type: GrantFiled: July 23, 1999Date of Patent: July 24, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Steven C. Avanzino, Stephen Keetai Park, Bharath Rangarajan, Jeffrey A. Shields, Larry Yu Wang, Guarionex Morales
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Patent number: 6265306Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining an opening in a layer of photoresist formed above a layer of dielectric material, heating the layer of photoresist to reduce the size of the opening in the layer of photoresist, and forming an opening in the layer of dielectric material that is defined by the reduced size opening in the layer of photoresist. The method further comprises removing the layer of photoresist and forming a conductive interconnection in the layer of dielectric material.Type: GrantFiled: January 12, 2000Date of Patent: July 24, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Gregory B. Starnes, Stephen Keetai Park
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Patent number: 6232635Abstract: An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.Type: GrantFiled: April 6, 2000Date of Patent: May 15, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Larry Yu Wang, Steven C. Avanzino, Jeffrey A. Shields, Stephen Keetai Park
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Patent number: 6107169Abstract: In a non-volatile semiconductor memory device, a top surface of a floating gate that is made of polysilicon is advantageously kept smooth to increase the uniformity of an overlying interpoly dielectric layer onto which a control gate is formed. The floating gate is doped after at least a portion of the overlying interpoly dielectric layer has been formed. Ion implantation techniques are employed to implant dopants through the overlying layer or layers and into the floating gate. Consequently, the potential for polysilicon grain growth at or near the top surface of the floating gate, which can lead to significant depressions in the overlying layers and data retention problems in the memory cell, is substantially reduced.Type: GrantFiled: August 14, 1998Date of Patent: August 22, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Stephen Keetai Park
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Patent number: 6100559Abstract: A graded cap layer that reduces the overall height of a layer stack and provides for increased process control during subsequent patterning of the layer stack, is described with a method of making the same. The graded cap layer is configured to function as a cap layer to prevent an underlying silicide layer from lifting, a barrier layer to prevent the underlying silicide layer from being oxidized during subsequent processes, a stop layer to prevent over-etching during subsequent self-aligned source (SAS) patterning processes, and/or an anti-reflective coating (ARC) to improve the resolution of subsequent patterning processes. The graded cap layer is a relatively thin layer of silicon oxynitride with varying concentrations of nitrogen. The cap layer is deposited in a single chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) chamber.Type: GrantFiled: August 14, 1998Date of Patent: August 8, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Stephen Keetai Park