Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: An integrated circuit device is disclosed that includes an sense amplifier having first and second input terminals, a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier, and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously.

Abstract: An integrated circuit device is disclosed that includes an sense amplifier having first and second input terminals, a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier, and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously.

Abstract: An amplifier circuit is disclosed having an amplifier with first and second input terminals. The amplifier circuit includes a first compensation capacitor coupled to the first input terminal and having a first capacitance, a second compensation capacitor coupled to the second input terminal and having a second capacitance, a first transistor coupled between the first compensation capacitor and a reference voltage and having a gate terminal that receives a first control signal, and a second transistor coupled between the second compensation capacitor and the reference voltage and having a gate terminal for receiving a second control signal. The amplifier circuit includes a programmable latch circuit arranged to provide the first and second control signals, wherein the first and second transistors are of the same conductivity type, and the first control signal and the second control signal are complementary signals with respect to each other.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

Abstract: An amplifier circuit is disclosed having an amplifier with first and second input terminals. The amplifier circuit includes a first compensation capacitor coupled to the first input terminal and having a first capacitance, a second compensation capacitor coupled to the second input terminal and having a second capacitance, a first transistor coupled between the first compensation capacitor and a reference voltage and having a gate terminal that receives a first control signal, and a second transistor coupled between the second compensation capacitor and the reference voltage and having a gate terminal for receiving a second control signal. The amplifier circuit includes a programmable latch circuit arranged to provide the first and second control signals, wherein the first and second transistors are of the same conductivity type, and the first control signal and the second control signal are complementary signals with respect to each other.

Abstract: An amplifier circuit is disclosed having an amplifier with first and second input terminals coupled to receive an input signal. A first compensation circuit is coupled to the first input terminal, and a second compensation circuit is coupled to the second input terminal. A programmable latch circuit is arranged to select one of the first and second compensation circuits.

Abstract: An amplifier circuit is disclosed having an amplifier with first and second input terminals coupled to receive an input signal. A first compensation circuit is coupled to the first input terminal, and a second compensation circuit is coupled to the second input terminal. A programmable latch circuit is arranged to select one of the first and second compensation circuits.

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines.

Abstract: A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines.

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.

Abstract: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.