Patents by Inventor Stephen L. Blinick
Stephen L. Blinick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130111106Abstract: Exemplary method, system, and computer program product embodiments for efficient track destage in secondary storage in a more effective manner, are provided. In one embodiment, by way of example only, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. Additional system and computer program product embodiments are disclosed and provide related advantages.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. BENHASE, Stephen L. BLINICK, Evangelos S. ELEFTHERIOU, Lokesh M. GUPTA, Robert HAAS, Xiao-Yu HU, Matthew J. KALOS, Ioannis KOLTSIDAS, Karl A. NIELSEN, Roman A. PLETKA
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Publication number: 20130111134Abstract: Various embodiments for movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor are provided. In one such embodiment, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes. Additional system and computer program product embodiments are disclosed and provide related advantages.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. BENHASE, Stephen L. BLINICK, Evangelos S. ELEFTHERIOU, Lokesh M. GUPTA, Robert HAAS, Xiao-Yu HU, Matthew J. KALOS, Ioannis KOLTSIDAS, Roman A. PLETKA
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Publication number: 20130111146Abstract: The population of data to be admitted into secondary data storage cache of a data storage system is controlled by determining heat metrics of data of the data storage system. If candidate data is submitted for admission into the secondary cache, data is selected to tentatively be evicted from the secondary cache; candidate data provided to the secondary data storage cache is rejected if its heat metric is less than the heat metric of the tentatively evicted data; and candidate data submitted for admission to the secondary data storage cache is admitted if its heat metric is equal to or greater than the heat metric of the tentatively evicted data.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin J. ASH, Michael T. BENHASE, Stephen L. BLINICK, Evangelos S. ELEFTHERIOU, Lokesh M. GUPTA, Robert HAAS, Xiao-Yu HU, Ioannis KOLTSIDAS, Roman A. PLETKA
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Patent number: 8407710Abstract: Systems and methods for scanning ports for work are provided. One system includes one or more processors, multiple ports, a first tracking mechanism, and a second tracking mechanism for tracking high priority work and low priority work, respectively. The processor(s) is/are configured to perform the below method. One method includes scanning the ports, finding high priority work on a port, and accepting or declining the high priority work. The method further includes changing a designation of the processor to TRUE in the first tracking mechanism if the processor accepts the high priority work such that the processor is allowed to perform the high priority work on the port. Also provided are computer storage mediums including computer code for performing the above method.Type: GrantFiled: October 14, 2010Date of Patent: March 26, 2013Assignee: International Business Machines CorporationInventors: Stephen L. Blinick, Steven E. Klein, Daniel W. Sherman
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Publication number: 20120254654Abstract: Methods are provided in which a standby server, a first main server, and a second main server to control shared input/output (I/O) adapters in a storage system are provided. The standby server is in communication with the first main server and the second main server, and the storage system is configured to operate as a dual node active system. The methods include activating the standby server in response to receiving a communication from the first main server of a fail mode of the second main server. Systems and physical computer storage media are also provided.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. BLINICK, Scott A. BREWER, Yu-Cheng HSU
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Publication number: 20120191904Abstract: A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein.Type: ApplicationFiled: March 26, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Lokesh M. Gupta, Yu-Cheng Hsu, Cheng-Chung Song
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Publication number: 20120096469Abstract: Systems and methods for scanning ports for work are provided. One system includes one or more processors, multiple ports, a first tracking mechanism, and a second tracking mechanism for tracking high priority work and low priority work, respectively. The processor(s) is/are configured to perform the below method. One method includes scanning the ports, finding high priority work on a port, and accepting or declining the high priority work. The method further includes changing a designation of the processor to TRUE in the first tracking mechanism if the processor accepts the high priority work such that the processor is allowed to perform the high priority work on the port. Also provided are computer storage mediums including computer code for performing the above method.Type: ApplicationFiled: October 14, 2010Publication date: April 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. BLINICK, Steven E. KLEIN, Daniel W. SHERMAN
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Publication number: 20120084514Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.Type: ApplicationFiled: October 4, 2010Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
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Patent number: 8136113Abstract: A sleep function capable of putting a fixed high-priority thread to sleep within a time-window is disclosed. After a sleep request has been made by a fixed high-priority thread via the sleep function, a determination is made whether or not the fixed high-priority thread is awoken before a requested sleep duration under the sleep request. If the fixed high-priority thread is awoken before the requested sleep duration, the number of tasks for the fixed high-priority thread to perform is increased in order to delay the start sleep time of the fixed high-priority thread from a point within a first time-window in which the sleep request was made to an end boundary of the first time-window.Type: GrantFiled: December 20, 2006Date of Patent: March 13, 2012Assignee: International Business Machines CorporationInventors: Stephen L. Blinick, Scott A. Brewer, Chiahong Chen, Daniel A. Heffley, Radha K. Ramachandran
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Patent number: 7934045Abstract: An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.Type: GrantFiled: June 9, 2009Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Stephen L. Blinick, John C. Elliott, Enrique Q. Garcia
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Publication number: 20110087837Abstract: A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein.Type: ApplicationFiled: October 10, 2009Publication date: April 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Lokesh M. Gupta, Yu-Cheng Hsu, Cheng-Chung Song
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Patent number: 7870417Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.Type: GrantFiled: April 20, 2007Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Stephen L. Blinick, Cheng-Chung Song, Carol Spanel, Andrew Dale Walls
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Publication number: 20100312942Abstract: An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.Type: ApplicationFiled: June 9, 2009Publication date: December 9, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, John C. Elliott, Enrique Q. Garcia
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Patent number: 7669050Abstract: A method to enable a user mode process to operate in a privileged execution mode is disclosed. Applicants' method provides an operating system comprising a privileged execution mode and a non-privileged execution mode, and a plurality of user mode strings operating in the non-privileged execution mode. The computing device receives a request from a first user mode string to operate in the privileged execution mode to perform one or more designated tasks. Applicants' method authorizes the first user mode string to operate in the privileged execution mode, and the first user mode string performs those one or more designated tasks using the privileged execution mode. Applicants' method continues to permit the first user mode string to operate in the privileged execution mode after completion of the one or more designated tasks.Type: GrantFiled: June 24, 2004Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Stephen L. Blinick, Yu-Cheng Hsu
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Patent number: 7596651Abstract: One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.Type: GrantFiled: May 29, 2007Date of Patent: September 29, 2009Assignee: International Business Machines CorporationInventors: Stephen L. Blinick, Carol Spanel, Andrew Dale Walls
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Publication number: 20090006809Abstract: Updating code of a single processor in a multi-processor system includes halting transactions processed by a first processor in the system and processing of transactions by a second processor in the system are maintained. The first processor then receives new code and an operating system running on the first processor is terminated whereby all processes and threads being executed by the first processor are terminated. Execution of a self-reset of the first processor is commenced and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor.Type: ApplicationFiled: June 27, 2007Publication date: January 1, 2009Applicant: IBM CORPORATIONInventors: Stephen L. Blinick, Chiahong Chen
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Publication number: 20080301345Abstract: One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.Type: ApplicationFiled: May 29, 2007Publication date: December 4, 2008Inventors: Stephen L. Blinick, Carol Spanel, Andrew Dale Walls
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Publication number: 20080263391Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Cheng-Chung Song, Carol Spanel, Andrew Dale Walls
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Publication number: 20080263255Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen L. Blinick, Cheng-Chung Song, Carol Spanel, Andrew Dale Walls
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Publication number: 20080155549Abstract: A sleep function capable of putting a fixed high-priority thread to sleep within a time-window is disclosed. After a sleep request has been made by a fixed high-priority thread via the sleep function, a determination is made whether or not the fixed high-priority thread is awoken before a requested sleep duration under the sleep request. If the fixed high-priority thread is awoken before the requested sleep duration, the number of tasks for the fixed high-priority thread to perform is increased in order to delay the start sleep time of the fixed high-priority thread from a point within a first time-window in which the sleep request was made to an end boundary of the first time-window.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Inventors: Stephen L. Blinick, Scott A. Brewer, Chiahong Chen, Daniel A. Heffley, Radha K. Ramachandran