Patents by Inventor Stephen M. Cea
Stephen M. Cea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153956Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.Type: ApplicationFiled: January 10, 2024Publication date: May 9, 2024Inventors: Seung Hoon SUNG, Cheng-Ying HUANG, Marko RADOSAVLJEVIC, Christopher M. NEUMANN, Susmita GHOSE, Varun MISHRA, Cory WEBER, Stephen M. CEA, Tahir GHANI, Jack T. KAVALIEROS
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Publication number: 20240105716Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Inventors: Leonard P. GULER, Sukru YEMENICIOGLU, Mohit K. HARAN, Stephen M. CEA, Charles H. WALLACE, Tahir GHANI, Shengsi LIU, Saurabh ACHARYA, Thomas O'BRIEN, Nidhi KHANDELWAL, Marie T. CONTE, Prabhjot LUTHRA
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Patent number: 11923370Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.Type: GrantFiled: September 23, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Seung Hoon Sung, Cheng-Ying Huang, Marko Radosavljevic, Christopher M. Neumann, Susmita Ghose, Varun Mishra, Cory Weber, Stephen M. Cea, Tahir Ghani, Jack T. Kavalieros
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Publication number: 20230317822Abstract: Embodiments described herein may be related to transistor structures where dimpled spacers, which may also be referred to as inner spacers or offset spacers, may be formed around gates within an epitaxial structure such that the epitaxial material adjacent to the dimpled spacer is uniform and/or defect free. In embodiments, forming the dimpled spacers occurs after epitaxial growth. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Inventors: Stephen M. CEA, Borna OBRADOVIC, Rishabh MEHANDRU, Jack T. KAVALIEROS
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Patent number: 11757026Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: October 16, 2020Date of Patent: September 12, 2023Assignee: Google LLCInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
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Publication number: 20230275085Abstract: Techniques are provided herein to form an integrated circuit having a grid of gate cut structures such that a gate cut structure exists between pairs of semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. Each of the gate cut structures may be formed at the same time in a grid-like pattern across the integrated circuit (or a portion thereof). Sidewall spacer structures on the sidewalls of the gate structure wrap around ends of each gate structure to form a given gate cut structure.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Applicant: Intel CorporationInventors: Leonard P. Guler, Sukru Yemenicioglu, Mohit K. Haran, Shengsi Liu, Robert Joachim, Dan S. Lavric, Stephen M. Cea
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Patent number: 11705518Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein Integrated circuit structures including increased transistor source/drain contact area using a sacrificial source/drain layer are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction).Type: GrantFiled: April 15, 2022Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Rishabh Mehandru, Stephen M. Cea, Biswajeet Guha, Tahir Ghani, William Hsu
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Publication number: 20230207651Abstract: Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion and a lower epitaxial extension portion.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Mohammad HASAN, Nitesh KUMAR, Rushabh SHAH, Anand S. MURTHY, Pratik PATEL, Tahir GHANI, Tricia MEYER, Cory BOMBERGER, Glenn A. GLASS, Stephen M. CEA, Anant H. JAHAGIRDAR
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Publication number: 20230207696Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits utilizing gate plugs to induce compressive channel strain. Other embodiments may be described or claimed.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Mohammad HASAN, Wonil CHUNG, Biswajeet GUHA, Saptarshi MANDAL, Pratik PATEL, Tahir GHANI, Stephen M. CEA, Anand S. MURTHY
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Patent number: 11676965Abstract: Fabrication techniques for NMOS and PMOS nanowires leveraging an isolated process flow for NMOS and PMOS nanowires facilitates independent (decoupled) tuning/variation of the respective geometries (i.e., sizing) and chemical composition of NMOS and PMOS nanowires existing in the same process. These independently tunable degrees of freedom are achieved due to fabrication techniques disclosed herein, which enable the ability to individually adjust the width of NMOS and PMOS nanowires as well as the general composition of the material forming these nanowires independently of one another.Type: GrantFiled: September 28, 2018Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Stephen M. Cea, Tahir Ghani, Anand S. Murthy, Biswajeet Guha
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Publication number: 20230170388Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.Type: ApplicationFiled: January 11, 2023Publication date: June 1, 2023Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
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Patent number: 11658183Abstract: Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.Type: GrantFiled: July 9, 2021Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow, Stephen M. Cea
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Publication number: 20230111329Abstract: Techniques and mechanisms to impose stress on a transistor which includes a channel region and a source or drain region each in a fin structure. In an embodiment, a gate structure of the transistor extends over the fin structure, wherein a first spacer portion is at a sidewall of the gate structure and a second spacer portion adjoins the first spacer portion. Either or both of two features are present at or under respective bottom edges of the spacer portions. One of the features includes a line of discontinuity on the fin structure. The other feature includes a concentration of a dopant in the second spacer portion being greater than a concentration of the dopant in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer, wherein stress on the channel region is imposed at least in part with the buffer layer.Type: ApplicationFiled: November 29, 2022Publication date: April 13, 2023Applicant: Intel CorporationInventors: Rishabh Mehandru, Stephen M. Cea, Tahir Ghani, Anand S. Murthy
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Publication number: 20230111689Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.Type: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Inventors: Stephen M. Cea, Annalisa Cappellani, Martin D. Giles, Rafael Rios, Seiyon Kim, Kelin J. Kuhn
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Publication number: 20230101725Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Debaleena NANDI, Mauro J. KOBRINSKY, Gilbert DEWEY, Chi-hing CHOI, Harold W. Kennel, Brian J. KRIST, Ashkar ALIYARUKUNJU, Cory BOMBERGER, Rushabh SHAH, Rishabh MEHANDRU, Stephen M. CEA, Chanaka MUNASINGHE, Anand S. MURTHY, Tahir GHANI
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Publication number: 20230095007Abstract: Integrated circuit structures having metal-containing source or drain structures, and methods of fabricating integrated circuit structures having metal-containing source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include a metal species diffused therein, the metal species further diffused partially into the vertical arrangement of horizontal nanowires.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Rishabh MEHANDRU, Stephen M. CEA, Aaron D. LILAK, Cory WEBER, Patrick KEYS, Navid PAYDAVOSI
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Publication number: 20230088753Abstract: Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Stephen M. Cea, Aaron D. Lilak, Patrick Keys, Cory Weber, Rishabh Mehandru, Anand S. Murthy, Biswajeet Guha, Mohammad Hasan, William Hsu, Tahir Ghani, Chang Wan Han, Kihoon Park, Sabih Omar
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Publication number: 20230046755Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.Type: ApplicationFiled: October 31, 2022Publication date: February 16, 2023Inventors: Rishabh MEHANDRU, Patrick MORROW, Ranjith KUMAR, Cory E. WEBER, Seiyon KIM, Stephen M. CEA, Tahir GHANI
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Patent number: 11581406Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.Type: GrantFiled: November 1, 2021Date of Patent: February 14, 2023Assignee: Daedalus Prime LLCInventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
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Patent number: 11557676Abstract: Techniques and mechanisms to impose stress on a transistor which includes a channel region and a source or drain region each in a fin structure. In an embodiment, a gate structure of the transistor extends over the fin structure, wherein a first spacer portion is at a sidewall of the gate structure and a second spacer portion adjoins the first spacer portion. Either or both of two features are present at or under respective bottom edges of the spacer portions. One of the features includes a line of discontinuity on the fin structure. The other feature includes a concentration of a dopant in the second spacer portion being greater than a concentration of the dopant in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer, wherein stress on the channel region is imposed at least in part with the buffer layer.Type: GrantFiled: September 29, 2017Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Rishabh Mehandru, Stephen M. Cea, Tahir Ghani, Anand S. Murthy