Patents by Inventor Stephen N. Grider
Stephen N. Grider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9773431Abstract: A secure microcontroller system comprising an integrated cache sub-system, crypto-engine, buffer sub-system and external memory is described according to various embodiments of the invention. The secure microcontroller incorporates block encryption methods to ensure that content communicated between the integrated microcontroller and external memory is protected and real-time performance of the system is maintained. Additionally, the microcontroller system provides a user-configurable memory write policy in which memory write protocols may be selected to balance data coherency and system performance.Type: GrantFiled: November 10, 2009Date of Patent: September 26, 2017Assignee: Maxim Integrated Products, Inc.Inventors: Edward Tang Kwai Ma, Stephen N. Grider
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Publication number: 20110113260Abstract: A secure microcontroller system comprising an integrated cache sub-system, crypto-engine, buffer sub-system and external memory is described according to various embodiments of the invention. The secure microcontroller incorporates block encryption methods to ensure that content communicated between the integrated microcontroller and external memory is protected and real-time performance of the system is maintained. Additionally, the microcontroller system provides a user-configurable memory write policy in which memory write protocols may be selected to balance data coherency and system performance.Type: ApplicationFiled: November 10, 2009Publication date: May 12, 2011Inventors: Edward Tang Kwai Ma, Stephen N. Grider
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Patent number: 6996725Abstract: Methods, systems, and arrangements enable increased security for a processor, including by implementing block encryption. The block may include multiple instructions and/or operations to be executed by the processor. The block may also include multiple bytes that are read into the processor byte by byte. Once a block-wide encrypted buffer has been filled from an external memory source, the block may be decrypted using an encryption algorithm (e.g., the Data Encryption Standard (DES), the triple DES, etc.), and the decrypted block may be forwarded to a decrypted buffer. The decrypted block may thereafter be moved into a cache, which may optionally be organized into an equivalent block width (e.g., for each way of a multi-way cache). Therefore, when a processing core/instruction decoder needs a new instruction, it may retrieve one from the cache, directly from the decrypted buffer, or from external memory (e.g., after undergoing decryption).Type: GrantFiled: August 16, 2001Date of Patent: February 7, 2006Assignee: Dallas Semiconductor CorporationInventors: Edward Tang Kwai Ma, Stephen N. Grider, Ann Little, legal representative, Wendell L. Little
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Patent number: 6868505Abstract: Methods, systems, and arrangements enable efficient reprogramming of a memory block of a microcontroller. Two blocks of memory each have a different logical location with respect to a processor of the microcontroller. The first memory may store vector information to be executed by the processor. The second memory may store data information. The logical location of each memory block is dependent on the value of a pre-determined bit in a specified register. When a user wishes to reprogram the contents of the first memory, the user enters new code into the second memory. Upon completion, the value of the pre-determined bit is changed, and the logical locations of the first and second memories are interchanged. In effect, the newly entered code from the second memory is accessed as if it were in the first memory (e.g., from an addressing perspective), and the processor may execute the new program (e.g., after the processor undergoes a system reset).Type: GrantFiled: August 7, 2001Date of Patent: March 15, 2005Assignee: Dallas Semiconductor CorporationInventors: Edward Tang Kwai Ma, Stephen N. Grider, Frank V. Taylor, III, Joseph P. Gorski, Andrew D. Jones, Ann Little, Wendell L. Little
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Patent number: 6691219Abstract: The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX1) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.Type: GrantFiled: August 7, 2001Date of Patent: February 10, 2004Assignee: Dallas Semiconductor CorporationInventors: Edward Tangkwai Ma, Frank V. Taylor, III, Stephen N. Grider, Wendell L. Little
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Publication number: 20030046563Abstract: Methods, systems, and arrangements enable increased security for a processor, including by implementing block encryption. The block may include multiple instructions and/or operations to be executed by the processor. The block may also include multiple bytes that are read into the processor byte by byte. Once a block-wide encrypted buffer has been filled from an external memory source, the block may be decrypted using an encryption algorithm (e.g., the Data Encryption Standard (DES), the triple DES, etc.), and the decrypted block may be forwarded to a decrypted buffer. The decrypted block may thereafter be moved into a cache, which may optionally be organized into an equivalent block width (e.g., for each way of a multi-way cache). Therefore, when a processing core/instruction decoder needs a new instruction, it may retrieve one from the cache, directly from the decrypted buffer, or from external memory (e.g., after undergoing decryption).Type: ApplicationFiled: August 16, 2001Publication date: March 6, 2003Applicant: Dallas SemiconductorInventors: Edward Tang Kwai Ma, Stephen N. Grider, Wendell L. Little, Ann Little
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Publication number: 20020194521Abstract: Methods, systems, and arrangements enable efficient reprogramming of a memory block of a microcontroller. Two blocks of memory each have a different logical location with respect to a processor of the microcontroller. The first memory may store vector information to be executed by the processor. The second memory may store data information. The logical location of each memory block is dependent on the value of a pre-determined bit in a specified register. When a user wishes to reprogram the contents of the first memory, the user enters new code into the second memory. Upon completion, the value of the pre-determined bit is changed, and the logical locations of the first and second memories are interchanged. In effect, the newly entered code from the second memory is accessed as if it were in the first memory (e.g., from an addressing perspective), and the processor may execute the new program (e.g., after the processor undergoes a system reset).Type: ApplicationFiled: August 7, 2001Publication date: December 19, 2002Applicant: Dallas Semiconductor CorporationInventors: Edward Tang Kwai Ma, Stephen N. Grider, Frank V. Taylor, Joseph P. Gorski, Andrew D. Jones, Wendell L. Little, Ann Little
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Publication number: 20020186086Abstract: An improved random number generator for micro-controllers is provided with multiple free running oscillators. These oscillators may be ring oscillators. They run at different frequencies. A phase difference between at least two of the oscillators provides the random number. The determination of a phase difference can be done by sampling the high speed oscillator using the lower speed oscillator. This sampling of the oscillators for the determination of a phase difference can be controlled by an oscillators as well. The random number is picked up from a shift register which provides feedback to a control circuit which can alter the frequency of one or more (including all) of the oscillators so that an increased randomness can be achieved. The random number from the shift register is loaded into a linear feedback shift register (LFSR) to generate independent uniform random data.Type: ApplicationFiled: June 12, 2001Publication date: December 12, 2002Applicant: Dallas Semiconductor CorporationInventors: Andreas Curiger, Stephen N. Grider
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Publication number: 20020156991Abstract: The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX1) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.Type: ApplicationFiled: August 7, 2001Publication date: October 24, 2002Inventors: Edward Tangkwai Ma, Frank V. Taylor, Stephen N. Grider, Wendell L. Little
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Parasitically powered microprocessor capable of transmitting data over a single data line and ground
Patent number: 6412072Abstract: An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include an integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.Type: GrantFiled: February 5, 2001Date of Patent: June 25, 2002Assignee: Dallas Semiconductor CorporationInventors: Wendell Little, Andreas Curiger, Stephen N. Grider, David A. Bunsey, James E. Bartling, Shyun Liu, Bradley M. Harrington -
Publication number: 20010011353Abstract: An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include an integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.Type: ApplicationFiled: February 5, 2001Publication date: August 2, 2001Applicant: Dallas Semiconductor CorporationInventors: Wendell Little, Andreas Curiger, Stephen N. Grider, David A. Bunsey, James E. Bartling, Shyun Liu, Bradley M. Harrington
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Patent number: 6219789Abstract: An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include an integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.Type: GrantFiled: September 15, 1998Date of Patent: April 17, 2001Assignee: Dallas Semiconductor CorporationInventors: Wendell Little, Andreas Curiger, Stephen N. Grider, David A. Bunsey, James E. Bartling, Shyun Liu, Bradley M. Harrington
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Patent number: 6038655Abstract: A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.Type: GrantFiled: January 16, 1997Date of Patent: March 14, 2000Assignee: Dallas Semiconductor CorporationInventors: Wendell L. Little, Stephen N. Grider, Joseph Wayne Triece
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Patent number: 5832207Abstract: An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.Type: GrantFiled: July 19, 1996Date of Patent: November 3, 1998Assignee: Dallas Semiconductor CorporationInventors: Wendell Little, Andreas Curiger, Stephen N. Grider, David A. Bunsey, James E. Bartling, Shyun Liu, Bradley M. Harrington
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Patent number: 5473271Abstract: A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.Type: GrantFiled: February 9, 1993Date of Patent: December 5, 1995Assignee: Dallas Semiconductor CorporationInventors: Wendell L. Little, Stephen N. Grider, Joseph W. Triece
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Patent number: 5381540Abstract: Interrupt circuitry for a processor comprises a plurality of interrupt inputs, an interrupt output, combinatorial logic with a plurality of combinatorial logic inputs connected to the plurality of interrupt inputs and with a combinatorial logic output connected to the interrupt output wherein an interrupt output signal at the interrupt output is a function of interrupt signals at the plurality of interrupt inputs; and an interrupt mode select connected to the combinatorial logic wherein an interrupt mode select signal from the interrupt mode select controls the function. The interrupt mode select signal from the interrupt mode select selects the function to be either AND or OR.Type: GrantFiled: December 2, 1992Date of Patent: January 10, 1995Assignee: Dallas Semiconductor CorporationInventors: Matthew K. Adams, Wendell L. Little, Stephen N. Grider
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Patent number: 5237699Abstract: A battery-backed microprocessor which enters a known state on power-down. This is achieved, even if the microprocessor does not permit a single-cycle reset, by providing clock intercept circuitry on chip. When system power failure is detected, the clock intercept circuitry disconnects the external clock, activates a reset command, and then generates several clock cycles using an internal clock generator after the reset command. As many clock cycles are generated as is needed, with the particular architecture being used, to reach a predetermined state.Type: GrantFiled: May 8, 1992Date of Patent: August 17, 1993Assignee: Dallas Semiconductor Corp.Inventors: Wendell L. Little, Stephen N. Grider
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Patent number: 5212774Abstract: Preferred embodiments include systems with two processors and an interconnected modem, one processor functioning as a control for both the modem and the second processor. This permits remote communication with the second processor for test or reconfiguration purposes.Type: GrantFiled: December 9, 1988Date of Patent: May 18, 1993Assignee: Dallas Semiconductor CorporationInventors: Stephen N. Grider, Don Folkes, Stephen M. Curry, Wendell L. Little
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Patent number: RE46956Abstract: Methods, systems, and arrangements enable increased security for a processor, including by implementing block encryption. The block may include multiple instructions and/or operations to be executed by the processor. The block may also include multiple bytes that are read into the processor byte by byte. Once a block-wide encrypted buffer has been filled from an external memory source, the block may be decrypted using an encryption algorithm (e.g., the Data Encryption Standard (DES), the triple DES, etc.), and the decrypted block may be forwarded to a decrypted buffer. The decrypted block may thereafter be moved into a cache, which may optionally be organized into an equivalent block width (e.g., for each way of a multi-way cache). Therefore, when a processing core/instruction decoder needs a new instruction, it may retrieve one from the cache, directly from the decrypted buffer, or from external memory (e.g., after undergoing decryption).Type: GrantFiled: December 9, 2015Date of Patent: July 17, 2018Assignee: Maxim Integrated Products, Inc.Inventors: Edward Tangkwai Ma, Stephen N. Grider, Wendell L. Little
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Patent number: RE48716Abstract: Methods, systems, and arrangements enable increased security for a processor, including by implementing block encryption. The block may include multiple instructions and/or operations to be executed by the processor. The block may also include multiple bytes that are read into the processor byte by byte. Once a block-wide encrypted buffer has been filled from an external memory source, the block may be decrypted using an encryption algorithm (e.g., the Data Encryption Standard (DES), the triple DES, etc.), and the decrypted block may be forwarded to a decrypted buffer. The decrypted block may thereafter be moved into a cache, which may optionally be organized into an equivalent block width (e.g., for each way of a multi-way cache). Therefore, when a processing core/instruction decoder needs a new instruction, it may retrieve one from the cache, directly from the decrypted buffer, or from external memory (e.g., after undergoing decryption).Type: GrantFiled: July 6, 2018Date of Patent: August 31, 2021Assignee: Maxim Integrated Products, Inc.Inventors: Edward Tangkwai Ma, Stephen N. Grider, Wendell L. Little