Abstract: A method and apparatus for communicating within a segmented network are generally disclosed.

Abstract: Method and apparatus for a trigger queue for a filter micro-code accelerator are described.

Abstract: An amplifier has a band pass response. The band pass response may be set by setting corner frequencies of low pass filters.

Abstract: Method and apparatus for a filter micro-code accelerator are described.

Abstract: An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.

Abstract: A cluster controller for controlling access to local memory and remote data cache in a multiple cluster computer system. In a multiple cluster computer system, a local memory in a cluster is part of the overall system address space. In order to manage local access as well as remote access to the local memory, the cluster controller maintains the responsibility of arbitrating the access to memory. Likewise, data from remote memory stored in the remote data cache is controlled by the cluster controller.

Abstract: A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Abstract: A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.

Abstract: An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.

Abstract: A cluster controller for controlling access to local memory and remote data cache in a multiple cluster computer system. In a multiple cluster computer system, a local memory in a cluster is part of the overall system address space. In order to manage local access as well as remote access to the local memory, the cluster controller maintains the responsibility of arbitrating the access to memory. Likewise, data from remote memory stored in the remote data cache is controlled by the cluster controller.

Abstract: An equal length symmetric computer bus topology. The equal length symmetric computer bus topology provides a bus signal path to a number of bus nodes. Each bus signal path extends from each node on the computer bus to a central junction point. The bus signal paths are of equal length and have identical electrical characteristics. The equal length symmetric computer bus topology minimizes the effect of transmission line reflections upon the bus signals. The equal length symmetric computer bus topology also causes very little clock skew.

Abstract: An apparatus and method for assigning memory address information in a computer system. The present invention relates to computer systems having a plurality of ports or slots for coupling boards or other apparatus accessible to a processor of the computer system. The computer system further comprises an address decoder electrically coupled with the ports and processor. The address decoder receives, preferably at the time the computer system is first powered on, memory size identifying information from each of the memory boards coupled with the plurality of slots. The address decoder assigns system address space to each of the individual memories.

Abstract: An apparatus and method for communicating characteristics about a memory module to a processor unit. A method and apparatus for communicating memory module characteristics, such as whether the module can communicate in a deterministic mode, memory size, memory speed, memory type and whether the memory is cachable to a processor. In the present invention, the processor asserts a request signal onto the system bus and the memory module corresponding to the address of the request respond with information regarding its characteristics.

Abstract: An improved method for accessing memory in a computer system using standard fast paged mode memory access for a second memory access where the second memory access is pending at the completion of a first memory access. However, if at the completion of a first memory access there is no pending memory request, the RAS line of the memory is deactivated allowing precharge during an idle state on the bus.

Abstract: An apparatus and method for allowing improved access to a memory by a processor utilizing a two strobed memory access protocol. The present invention discloses a method and apparatus for allowing a processor to request access to a memory over a communication bus, the processor retains control of the bus, and access to the memory, during the period of time it asserts an access strobe signal. The memory will respond to write or read requests to the memory during this period of time and the processor may address memory locations in a given page of the memory during this period of time. These accesses which occur during this period of time are initiated or terminated by a second access strobe signal while the first strobe remains active. This allows for more improved memory access times by holding it active during this multiple access window.

Abstract: A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.