Abstract: Quality control testing for a batch of electronic modules. A series of tests are performed on manufactured electronic modules, including tests sensitive to the failure rate of previously tested modules. Specifically, a first test comprised of two phases is performed on the module batch. Further screening is then performed responsive to detection of a wire sweep failure in a subset of failed modules from the first test phase. The further screening is on modules that passed the first test phase and excludes modules that failed the first test phase.

Abstract: Quality control testing for a batch of electronic modules. A series of tests are performed on manufactured electronic modules, including tests sensitive to the failure rate of previously tested modules. Specifically, a first test comprised of two phases is performed on the module batch. Further screening is then performed responsive to detection of a wire sweep failure in a subset of failed modules from the first test phase. The further screening is on modules that passed the first test phase and excludes modules that failed the first test phase.

Abstract: Quality control testing for a batch of electronic modules. A series of tests are performed on manufactured electronic modules, including tests sensitive to the failure rate of previously tested modules. Specifically, a first test comprised of two phases is performed on the module batch. Further screening is then performed responsive to detection of a wire sweep failure in a subset of failed modules from the first test phase. The further screening is on modules that passed the first test phase and excludes modules that failed the first test phase.

Abstract: The present invention relates to a tray for storing a semiconductor device of a ball grid array type. More specifically, a tray structure is provided, which includes a pocket formed in the tray for holding the semiconductor device, the pocket includes sidewalls having an upper portion and a lower portion, and a shelf portion located between the upper and lower portions of the sidewalls. The shelf portion extends horizontally inwardly from the upper portion of the sidewalls to support a portion of peripheral edges of the semiconductor device. The plurality of solder balls along the peripheral edges are spaced apart from the lower portion of the sidewalls of the pocket and an inner edge of the shelf portion when one of the opposing sides of the semiconductor device abuts the upper portion of the pocket.

Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

Abstract: An electronic device. The device including a module having opposite top surface and bottom surfaces; a first set of pads on the top surface of the module and a second set of pads on the bottom surface of the module substrate, wires within the module electrically connecting the first set of pads to the second set of pads; a set of solder interconnects in electrical and physical contact with a the second set of module pads; and a dielectric underfill layer formed on the bottom surface of the module, the underfill layer filling the space between lower regions of the solder interconnects of the set of solder interconnects, upper regions of the solder interconnects of the set of solder interconnects extending past a top surface of the underfill layer.

Abstract: A method of attaching an integrated circuit chip to a module and a resultant structure. The method includes placing a solder bump tape between the chip and the module, the solder bump tape including an array of solder columns embedded in a dielectric sheet; aligning and contacting top surfaces of solder columns with respective chip pads of an array of chip pads of the chip and aligning and contacting bottom surfaces of the solder columns with respective module pads of an array of module pads; and reflowing the solder columns to form solder interconnections between chip pads and respective module pads.

Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

Abstract: An electronic device and a method of forming the device. The device including a module having opposite top surface and bottom surfaces; a first set of pads on the top surface of the module and a second set of pads on the bottom surface of the module substrate, wires within the module electrically connecting the first set of pads to the second set of pads; a set of solder interconnects in electrical and physical contact with a the second set of module pads; and a dielectric underfill layer formed on the bottom surface of the module, the underfill layer filling the space between lower regions of the solder interconnects of the set of solder interconnects, upper regions of the solder interconnects of the set of solder interconnects extending past a top surface of the underfill layer.