Abstract: In one embodiment, a digital circuit element has a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element. In another embodiment, a digital circuit element may include an input node, an output node, and at least one gate coupling the input node and the output node. A plurality of possible voltage transition curves may be associated with a corresponding change of a first voltage at the input node over time, each voltage transition curve being determined by a corresponding supply voltage and the curves intersecting within a relatively narrow range of voltages. The gate may be operable to change a second voltage at the output node in response to the first voltage reaching a threshold voltage of the gate, and the threshold voltage may be set within the relatively narrow range of voltages in which the voltage transition curves intersect in order to reduce the dependence of the propagation delay on the supply voltage.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: In one embodiment, a digital circuit element has a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element. In another embodiment, a digital circuit element may include an input node, an output node, and at least one gate coupling the input node and the output node. A plurality of possible voltage transition curves may be associated with a corresponding change of a first voltage at the input node over time, each voltage transition curve being determined by a corresponding supply voltage and the curves intersecting within a relatively narrow range of voltages. The gate may be operable to change a second voltage at the output node in response to the first voltage reaching a threshold voltage of the gate, and the threshold voltage may be set within the relatively narrow range of voltages in which the voltage transition curves intersect in order to reduce the dependence of the propagation delay on the supply voltage.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: A voting circuit (34) comprises a first variable delay (60) operable to receive a first set of signals in a clock signal and to determine a first delay based on the first set of signals. The first variable delay (60) generates a first delayed output in response to the first delay of the clock signal. A second variable delay (62) is operable to receive a second set of signals and a clock signal and to determine a second delay based on the second set of signals. The second variable delay (62) generates a second delayed output in response to the second delay of the clock signal. A latch (64) is connected to the first and second variable delays. The latch (64) is operable to receive the first and second delayed outputs and to generate a latched voting output in response to at least one of the first and second delayed outputs.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: A low noise system for transmitting data includes a data bus (12) and a transmitting system (14). The data bus (12) has a plurality of data lines (20) and parity line (22). The transmitting system (14) is coupled to the data bus (12) and operable to receive a data set, store a previously adjusted data set transmitted on the data lines, generate a parity signal based on the data set and the previously adjusted data set and generate an adjusted data set based on the data and the parity signal. The adjusted data set is transmitted on the data lines (20) and the parity signal is transmitted on the parity line (22).

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: Circuitry is provided for controlling current in an electronic circuit by determining a rating of the electronic circuit in response to a measured propagation of a signal during a fixed period of time and by controlling current through an output node of the electronic circuit in response to the rating. The current may be controlled by magnitude or by rate of change with respect to time. By controlling current in response to the rating, timing disparities between and within electronic circuits are reduced, and signal noise in an electronic circuit is reduced by lowering unnecessary amounts of current driving the output node and/or by lowering unnecessarily high DI/DT rates of change in current driving the output node.

Abstract: An output circuit is provided which contains voltage control circuitry (14) which drives the gates of the output transistors (18, 20) such that the change in current remains relatively constant. The desired voltage output of the voltage control circuitry (14) can be implemented for a CMOS device using N channel and P channel transistors having their gates connected to V.sub.cc and ground respectively. The amount of current control may be adjusted to compensate for environmental conditions such as temperature or voltage supply either dynamically or prior to use.

Abstract: The disclosure relates to a circuit and method of reducing inductive voltage spikes caused by an abrupt change in current by an output transistor, by providing an input node for receiving an input voltage signal, providing an output node, providing a first transistor coupled to the output node, receiving a predetermined voltage at the input node, controlling voltage control circuitry coupled between the input node and the first transistor and responsive to the predetermined voltage at the input node to control the voltage driving the first transistor with respect to time to provide a constant rate of change of current with respect to time in the first transistor and providing a second transistor coupled to the output node in parallel with the first transistor which turns on prior to the first transistor.

Abstract: There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from negative voltage levels to positive voltage levels. The circuit includes voltage control levels for precisely controlling voltage as a function of temperature, all while only using positive voltage levels on the conversion circuit.

Abstract: An output circuit is provided which contains voltage control circuitry (14) which drives the gates of the output transistors (18,20) such that the change in current remains relatively constant. The desired voltage output of the voltage control circuitry (14) can be implemented for a CMOS device using N channel and P channel transistors having their gates connected to V.sub.cc and ground respectively. The amount of current control may be adjusted to compensate for environmental conditions such as temperature or voltage supply either dynamically or prior to use.

Abstract: A output circuit is provided which contains voltage control circuitry (14) which drives the gates of the output transistors (18,20) such that the change in current remains relatively constant. The desired voltage output of the voltage control circuitry (14) can be implemented for a CMOS device using N-channel and P-channel transistors having their gates connected to V.sub.cc and ground respectively.

Abstract: An improved differential amplifier having improved immunity to signals on the power supply terminals (32,34) thereof. The low impedance path between the power supply terminals (32,34) of the amplifier and the second gain stage transistor (24) is removed and connected to a low noise reference. The source of the transistor (24) is provided as an output terminal (23) of the amplifier and can be optionally connected to any low noise reference. High impedance input current mirrors (47,55,63,67) are connected between the supply voltage rails (33,35) and the amplifier, thereby further reducing the amplifier's susceptibility to noise.

Abstract: A temperature compensated, phase tolerant sense amplifier for use in a magnetic bubble memory system in which current is applied to the detector resistors only during a bubble detect operation.

Abstract: A circuit is disclosed for driving a piezo ceramic device as used in smoke alarms or other audio warning devices. The circuit detects the resonant frequency of the piezo horn and provides an alternating current at the resonant frequency of the horn for maximum sound output. The circuit has a self starting resonant oscillation characteristic. Two pairs of switches act in concert to alternatingly connect each side of the piezo horn to the supply voltage and ground, causing the maximum voltage swing across the piezo horn to be effectively twice the available power supply voltage.

Abstract: A digital data sense amplifier is disclosed for detecting small signal outputs from a storage media or from input sensors and comprises a differential amplifier whose outputs are coupled via two capacitors to an offset circuit which generates two offsets which in turn are fed to two comparators, one for a positive signal threshold and one for a negative signal threshold. This results in peak to peak data sensing in a noisy signal environment. An alternative embodiment differentiates an inputted analog signal and outputs a digital representation of the first derivative, or rate of change of said analog signal.

Abstract: An improved MOS current mirror wherein the mirror transistors are biased to operate in the saturated region near the boundary between the linear and the saturated regions to maximize the voltage gain and the power supply rejection ratio while maintaining a high output impedance.

Abstract: A temperature compensated, phase tolerant sense amplifier for use in a magnetic bubble memory system in which current is applied to the detector resistors only during a bubble detect operation.