Abstract: A non-volatile MOS memory array cell in which polycide bit lines are connected via self-aligned buried contacts to shared drain regions and run continuously over, but are electrically isolated from, shared source regions. Self-aligned buried contact windows are obtained by depositing and anisotropically etching-back an oxide layer with a non-critical mask. Preferably N-type doped polycide provides bit lines and self-aligned buried contacts with low resistance, low current leakage to the substrate, and good step coverage without bit line bridging. It is expected that this invention will make it feasible to manufacture high density non-volatile memory array products with good yield rates.

Abstract: An EPROM structure incorporating Vss isolation transistors having gates on wordlines shared by respective rows of conventional self-aligned EPROM cells, and having source and drain regions connected in series between EPROM cell source regions and the ground Vss terminal. An isolation transistor becomes conductive only when an EPROM cell sharing its wordline is selected. During programming, otherwise possible leakage current through unselected cells sharing the selected bitline is blocked by the Vss isolation transistor. Only one unselected adjacent cell, which shares a common source region with the selected cell, can leak. This leakage, if properly suppressed and compensated, has no disturbance on the unselected or selected cells during array programming.

Abstract: An EPROM structure incorporating Vss isolation transistors having gates on wordlines shared by respective rows of conventional self-aligned EPROM cells, and having source and drain regions connected in series between EPROM cell source regions and the ground Vss terminal. An isolation transistor becomes conductive only when an EPROM cell sharing its wordline is selected. During programming, otherwise possible leakage current through unselected cells sharing the selected bitline is blocked by the Vss isolation transistor. Only one unselected adjacent cell, which shares a common source region with the selected cell, can leak. This leakage, if properly suppressed and compensated, has no disturbance on unselected or selected cells during array programming. The EPROM cell drain punchthrough voltage and channel length can thus be reduced to obtain an EPROM cell with a low threshold voltage, low drain programming voltage, short programming time, low cell junction and bitline capacitance, and high read current.

Abstract: An LDD MOSFET structure in which gate sidewall spacers are formed of polycrystalline silicon and electrically shorted to the gate to extend gate control over the LDD region surface oxide and thereby reduce and control interface charge trapping without increasing substrate currents.