Abstract: A system and method for optimized specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the “intensity instruction” retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process. In one embodiment, the invention may be implemented using PowerPC™ assembly and VMX™ or Altivec™ instructions. In this embodiment, the intensity instruction may be represented as a “vspecefp” instruction, which stands for a “vector specular estimate floating point” instruction.

Abstract: In a first aspect, a first method is provided for pipelined processing. The first method includes the steps of (1) receiving a first instruction in an in-order execution processing pipeline; and (2) receiving a second instruction in the in-order execution processing pipeline before execution of the first instruction completes. The second instruction depends on a control signal related to the first instruction. Numerous other aspects are provided.

Abstract: The present invention provides for implementing a base two logarithmic estimation function in a general purpose processor. The present invention provides for partitioning an input value into a biased exponent value and a mantissa. Whether the biased exponent value is negative is determined. A first intermediate value from the mantissa is generated using custom combinational logic. A second intermediate value from the mantissa is generated using custom combinational logic. An unnormalized result fraction value from the first and second intermediate value and the mantissa is generated using custom combinational logic. This unnormalized result fraction and the unbiased exponent of the input are concatenated and normalized to form the final result.

Abstract: A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.