Patents by Inventor Stephen Szulewski
Stephen Szulewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8171442Abstract: A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net and determining a percentage of the identified net to be partially isolated.Type: GrantFiled: September 11, 2009Date of Patent: May 1, 2012Assignee: International Business Machines CorporationInventors: Alexandra Echegaray, Heidi L. Lagares, Douglas S. Search, Stephen Szulewski
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Publication number: 20110066989Abstract: A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net and determining a percentage of the identified net to be partially isolated.Type: ApplicationFiled: September 11, 2009Publication date: March 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexandra Echegaray, Heidi L. Lagares, Douglas S. Search, Stephen Szulewski
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Patent number: 7487484Abstract: A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Initial placement of the circuitry is determined in response to the composite net weight.Type: GrantFiled: August 22, 2006Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: James J. Curtin, Ray Raphy, Stephen Szulewski
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Publication number: 20080046850Abstract: An integrated circuit chip has more “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one.Type: ApplicationFiled: October 23, 2007Publication date: February 21, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Curtin, Kevin Mcllvain, Ray Raphy, Douglas Search, Stephen Szulewski
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Patent number: 7305644Abstract: More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one.Type: GrantFiled: May 16, 2005Date of Patent: December 4, 2007Assignee: International Business Machines CorporationInventors: James J. Curtin, Kevin M. McIlvain, Ray Raphy, Douglas S. Search, Stephen Szulewski
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Patent number: 7290233Abstract: A circuit design method utilizes existing late mode worst case slack calculation functions inherent in timing path trace algorithms which only need to record the worst arrival and worst required arrival times at each netlist node as traced paths. Because of this, most individual path tracing is curtailed due to the likelihood that a more critical arrival or required arrival time has already been recorded at a given netlist node. Worst case slacks are then determined by subtracting the worst case arrival time from the worst case required arrival time. In this manner, worst case slack values are calculated for the entire netlist within a reasonable amount of time. The method uses these existing functions by querying the worst case slack at each netlist node under varied timing model scenarios. These varied timing model scenarios include altering the cell and net delays and arrival times in the model.Type: GrantFiled: May 16, 2005Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: James J. Curtin, Kevin M. McIlvain, Ray Raphy, Douglas S. Search, Stephen Szulewski
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Publication number: 20060277515Abstract: A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Initial placement of the circuitry is determined in response to the composite net weight.Type: ApplicationFiled: August 22, 2006Publication date: December 7, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Curtin, Ray Raphy, Stephen Szulewski
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Patent number: 7120888Abstract: A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Initial placement of the circuitry is determined in response to the composite net weight.Type: GrantFiled: July 12, 2004Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: James J. Curtin, Ray Raphy, Stephen Szulewski
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Publication number: 20060015836Abstract: More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one..Type: ApplicationFiled: May 16, 2005Publication date: January 19, 2006Applicant: International Business Machines CorporationInventors: James Curtin, Kevin McIlvain, Ray Raphy, Douglas Search, Stephen Szulewski
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Publication number: 20060010415Abstract: A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Initial placement of the circuitry is determined in response to the composite net weight.Type: ApplicationFiled: July 12, 2004Publication date: January 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Curtin, Ray Raphy, Stephen Szulewski
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Publication number: 20060010411Abstract: A circuit design method utilizes existing late mode worst case slack calculation functions inherent in timing path trace algorithms which only need to record the worst arrival and worst required arrival times at each netlist node as traced paths. Because of this, most individual path tracing is curtailed due to the likelihood that a more critical arrival or required arrival time has already been recorded at a given netlist node. Worst case slacks are then determined by subtracting the worst case arrival time from the worst case required arrival time. In this manner, worst case slack values are calculated for the entire netlist within a reasonable amount of time. The method uses these existing functions by querying the worst case slack at each netlist node under varied timing model scenarios. These varied timing model scenarios include altering the cell and net delays and arrival times in the model.Type: ApplicationFiled: May 16, 2005Publication date: January 12, 2006Applicant: International Business Machines CorporationInventors: James Curtin, Kevin McIlvain, Ray Raphy, Douglas Search, Stephen Szulewski
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Patent number: 6792609Abstract: A system and method to create child objects from parent objects in an action diary. Child objects are created with increasing specificity regarding a system situation. A method is provided for associating an action diary based on the parent class of an object, even if there are no instances of objects of the parent class. A knowledge expert creates an action diary and associate that diary with a parent class object. The children of that class have the class generic action diary available to assist the operator in handling new situations. As the operators improve the handling of a specific situation, a new action diary is created by including information and actions in from the original action diary and can be associated with the specific child object. Thus the evolution of knowledge can orderly proceed from a general type to a specific.Type: GrantFiled: November 16, 2000Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: Margaret Gardner MacPhail, Richard Stephen Szulewski