Abstract: Various approaches for the packet processing, and the use of templates for generating modification commands for packet processing, are discussed herein. In an example, operations performed by network packet processing circuitry include: obtaining a stream of packets; obtaining a packet modification template that provides at least one command to insert content within the packets and change the packets according to an output format of a network protocol; receiving parameters to modify the packet modification template; and applying the packet modification template to modify the packets. In further examples, application of the packet modification template is performed using multiple processing components arranged in parallel groups of serial pipelines, each of the serial pipelines applying a portion of the packet modification template within at least a first stage and a second stage in each of the serial pipelines.

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data, wherein the sensor data is captured by a plurality of sensors within an educational environment. The processor is to: access the sensor data captured by the plurality of sensors; identify a student within the educational environment based on the sensor data; detect a plurality of events associated with the student based on the sensor data, wherein each event is indicative of an attention level of the student within the educational environment; generate a report based on the plurality of events associated with the student; and send the report to a third party associated with the student.

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

Abstract: Examples described herein relate to an encoder circuitry to apply one of multiple lossless data compression schemes on input data. In some examples, to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme. In some examples, content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme. In some examples, an applicable hash function is configured based on the applied compression scheme. In some examples, a number of searches are made for a byte position. In some examples, the encoder circuitry includes a hash table look-up and a bank decoder. In some examples, the hash table look-up is to generate a hash index to identify an address of an entry in the search window. In some examples, the bank decoder is to select a bank based on the hash index.

Abstract: Disclosed is a source host including a processor. The processor operates a virtual machine (VM) to communicate network traffic over a communication link. The processor also initiates migration of the VM to a destination host. The processor also suspends the VM during migration of the VM to the destination host. The source host also includes a live migration circuit coupled to the processor. The live migration circuit manages a session associated with the communication link while the VM is suspended during migration. The live migration circuit buffers changes to a session state and transfers the buffered session state changes to the destination host for replay after the VM is reactivated on the destination host. The live migration circuit keeps the sessions alive during migration to alleviate connection losses.

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

Abstract: Discussed herein are component redundancy systems, devices, and methods. A method to transfer a workload from a first component to a second component of a same device may include monitoring a wear indicator associated with the first component, and in response to an indication that the first component is stressed based on the wear indicator, transferring a workload of the first component to the second component.

Abstract: Embodiments of a system and method for dynamic hardware acceleration are generally described herein. A method may include identifying a candidate task from a plurality of tasks executing in an operating environment, the operating environment within a hardware enclosure, the candidate task amenable to hardware optimization, instantiating, in response to identifying the candidate task, a hardware component in the operating environment to perform hardware optimization for the task, the hardware component being previously inaccessible to the operating environment, and executing, by the operating environment, a class of tasks amenable to the hardware optimization on the hardware component.

Abstract: Examples described herein relate to an apparatus comprising a central processing unit (CPU) and an encoding accelerator coupled to the CPU, the encoding accelerator comprising an entropy encoder to determine normalized probability of occurrence of a symbol in a set of characters using a normalized probability approximation circuitry, wherein the normalized probability approximation circuitry is to output the normalized probability of occurrence of a symbol in a set of characters for lossless compression. In some examples, the normalized probability approximation circuitry includes a shifter, adder, subtractor, or a comparator. In some examples, the normalized probability approximation circuitry is to determine normalized probability by performance of non-power of 2 division without computation by a Floating Point Unit (FPU). In some examples, the normalized probability approximation circuitry is to round the normalized probability to a decimal.

Abstract: Various systems and methods for implementing an edge computing system to realize 5G network slices with blockchain traceability for informed 5G service supply chain are disclosed. A system configured to track network slicing operations includes memory and processing circuitry configured to select a network slice instance (NSI) from a plurality of available NSIs based on an NSI type specified by a client node. The available NSIs uses virtualized network resources of a first network resource provider. The client node is associated with the selected NSI. The utilization of the network resources by the plurality of available NSIs is determined using an artificial intelligence (AI)-based network inferencing function. A ledger entry of associating the selected NSI with the client node is recorded in a distributed ledger, which further includes a second ledger entry indicating allocations of resource subsets to each of the NSIs based on the utilization.

Abstract: In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.

Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.

Abstract: An input/output (I/O) device arranged to receive an information element including a payload, determine control information from the information element, classify the information element based on the control information, and issue a write to one of a plurality of computer-readable media based on the classification of the information element, the write to cause the payload to be written to the one of the plurality of computer-readable media.

Abstract: Technologies for monitoring service level agreement (SLA) performance in an end-to-end SLA monitoring architecture include a network functions virtualization (NFV) SLA controller configured to manage SLA agents initialized in various network processing components of the end-to-end SLA monitoring architecture. To do so, the NFV SLA controller is configured to provide instruction to the SLA agents indicating which types of telemetry data to monitor and receive the requested telemetry data, as securely collected and securely packaged by the SLA agents. The NFV SLA controller is further configured to securely analyze the received telemetry data to determine one or more performance metrics and compare performance benchmarks against the performance metrics to generate an SLA report that includes the results of the comparison. Other embodiments are described and claimed.

Abstract: Technologies for simulating service degradation in telemetry data include a simulator device. The simulator device is to identify a telemetry data stream from a production system to a first management system. The simulator device is also to fork a copy of the telemetry data stream for transmission to a second management system, determine perturbations associated with a determined service degradation type, and apply the perturbations to the forked telemetry data stream. Other embodiments are also described and claimed.

Abstract: In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.

Abstract: A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.

Abstract: A compression engine includes sets of independent search engines. The sets of independent search engines concurrently perform searches for a longest match in a stream of uncompressed data. The searches are distributed amongst the sets of independent search engines on byte boundaries to load balance the use of the search engines.

Abstract: System and techniques for a multi-class Long Range Lower Power (LRLP) access point (AP) multifactor intelligent agent control are described herein. A station (STA) association at the AP is received. Here, the association includes Class Identifier (ID) information. The Class ID information encompasses a set of communication parameters. A schedule of LRLP and non-LRLP STAs with associations at the AP is maintained. A transceiver chain is modified based on the schedule and the set of communication parameters to complete a communication with the STA.