Patents by Inventor Stephen T. Quay
Stephen T. Quay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10503841Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: GrantFiled: May 28, 2019Date of Patent: December 10, 2019Assignee: International Business Machines CorporationInventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Patent number: 10496764Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: GrantFiled: May 28, 2019Date of Patent: December 3, 2019Assignee: International Business Machines CorporationInventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20190278873Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20190278874Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Patent number: 10372836Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: GrantFiled: December 20, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Patent number: 10372837Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: GrantFiled: February 14, 2018Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Patent number: 10346558Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: GrantFiled: June 22, 2017Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20180373814Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: December 20, 2017Publication date: December 27, 2018Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20180373813Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: June 22, 2017Publication date: December 27, 2018Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20180373815Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: February 14, 2018Publication date: December 27, 2018Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Patent number: 9875326Abstract: A mechanism is provided for addressing coupled noise-based violations. For each net in an integrated circuit (IC) design, a determination is made as to whether an associated delta wire delay is below a predetermined threshold. Responsive to the associated delta wire delay failing to be below the predetermined threshold, a subset of nets is formed. For each net in the subset of nets, a stage delay side model of the net is adjusted to emulate a noise impact on timing of the net and an optimization is applied using the stage delay side model of the net. A full retiming of the set of nets is then performed. For each net in the subset of nets a determination is made as to whether the net has degraded slack and, responsive to the net having degraded slack, the applied optimization is backed out.Type: GrantFiled: December 4, 2015Date of Patent: January 23, 2018Assignee: International Business Machines CorporationInventors: Charles J. Alpert, William E. Dougherty, Jr., Zhuo Li, Stephen T. Quay, Ying Zhou
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Publication number: 20170161407Abstract: A mechanism is provided for addressing coupled noise-based violations. For each net in an integrated circuit (IC) design, a determination is made as to whether an associated delta wire delay is below a predetermined threshold. Responsive to the associated delta wire delay failing to be below the predetermined threshold, a subset of nets is formed. For each net in the subset of nets, a stage delay side model of the net is adjusted to emulate a noise impact on timing of the net and an optimization is applied using the stage delay side model of the net. A full retiming of the set of nets is then performed. For each net in the subset of nets a determination is made as to whether the net has degraded slack and, responsive to the net having degraded slack, the applied optimization is backed out.Type: ApplicationFiled: December 4, 2015Publication date: June 8, 2017Inventors: Charles J. Alpert, William E. Dougherty, JR., Zhuo Li, Stephen T. Quay, Ying Zhou
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Patent number: 9092591Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.Type: GrantFiled: April 10, 2014Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Charles J. Alpert, Robert M. Averill, III, Eric J. Fluhr, Zhuo Li, Tuhin Mahmud, Jose L. P. Neves, Stephen T. Quay, Chin Ngai Sze, Yaoguang Wei
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Patent number: 9038009Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.Type: GrantFiled: December 9, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Robert M. Averill, III, Zhuo Li, Jose L. P. Neves, Stephen T. Quay
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Patent number: 8881089Abstract: A system, process, etc. according to some embodiments, which includes operations that include selecting one of a plurality of solutions (“selected solution”) for optimization of an integrated circuit design during physical synthesis. The operations can further include performing on the selected solution a fast evaluation of a specific metric without updating design documents (e.g., without updating a netlist or metric map). If the evaluation of the specific metric is non-satisfactory, then the candidate solution is rejected. If the evaluation of the specific metric is satisfactory, then a design document is updated and a full evaluation of the specific metric (and other metrics) can be performed.Type: GrantFiled: December 17, 2013Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Glenn R. Bee, Zhuo Li, Tuhin Mahmud, Stephen T. Quay, Lakshmi N. Reddy, Chin Ngai Sze, Yaoguang Wei
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Publication number: 20140223397Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.Type: ApplicationFiled: April 10, 2014Publication date: August 7, 2014Applicant: International Business Machines CorporationInventors: Charles J. Alpert, Robert M. Averill, III, Eric J. Fluhr, Zhuo Li, Tuhin Mahmud, Jose L.P. Neves, Stephen T. Quay, Chin Ngai Sze, Yaoguang Wei
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Publication number: 20140195998Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles J. Alpert, Robert M. Averill, III, Eric J. Fluhr, Zhuo Li, Tuhin Mahmud, Jose L.P. Neves, Stephen T. Quay, Chin Ngai Sze, Yaoguang Wei
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Patent number: 8769468Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.Type: GrantFiled: January 9, 2013Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Charles J. Alpert, Robert M. Averill, III, Eric J. Fluhr, Zhuo Li, Tuhin Mahmud, Jose L. P. Neves, Stephen T. Quay, Chin Ngai Sze, Yaoguang Wei
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Publication number: 20140101629Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.Type: ApplicationFiled: December 9, 2013Publication date: April 10, 2014Applicant: International Business Machines CorporationInventors: Charles Jay Alpert, Robert M. Averill, III, Zhuo Li, Jose L. P. Neves, Stephen T. Quay
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Patent number: 8640075Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.Type: GrantFiled: June 1, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Robert M. Averill, III, Zhuo Li, Jose L. P. Neves, Stephen T. Quay